Statistical Power Supply Dynamic Noise Prediction in Hierarchical Power Grid and Package Networks

One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, /a priori dynamic voltage drop/evaluation is the focus of this work. It takes into account transient currents and on-chip and package /RLC/ parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable result

On-Chip Power Supply Noise: Scaling, Suppression and Detection

Design metrics such as area, timing and power are generally considered as the primary criteria in the design of modern day circuits, however, the minimization of power supply noise, among other noise sources, is appreciably more important since not only can it cause a degradation in these parameters but can cause entire chips to fail. Ensuring the integrity of the power supply voltage in the power distribution network of a chip is therefore crucial to both building reliable circuits as well as preventing circuit performance degradation. Power supply noise concerns, predicted over two decades ago, continue to draw significant attention, and with present CMOS technology projected to keep on scaling, it is shown in this work that these issues are not expected to diminish. This research also considers the management and on-chip detection of power supply noise. There are various methods of managing power supply noise, with the use of decoupling capacitors being the most common technique for suppressing the noise. An in-depth analysis of decap structures including scaling effects is presented in this work with corroborating silicon results. The applicability of various decaps for given design constraints is provided. It is shown that MOS-metal hybrid structures can provide a significant increase in capacitance per unit area compared to traditional structures and will continue to be an important structure as technology continues to scale. Noise suppression by means of current shifting within the clock period of an ALU block is further shown to be an additional method of reducing the minimum voltage observed on its associated supply. A simple, and area and power efficient technique for on-chip supply noise detection is also proposed

Effective network grid synthesis and optimization for high performance very large scale integration system design

制度:新 ; 文部省報告番号:甲2642号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新480

ULTRALOW-POWER, LOW-VOLTAGE DIGITAL CIRCUITS FOR BIOMEDICAL SENSOR NODES

Ph.DDOCTOR OF PHILOSOPH

Emerging Converter Topologies and Control for Grid Connected Photovoltaic Systems

Continuous cost reduction of photovoltaic (PV) systems and the rise of power auctions resulted in the establishment of PV power not only as a green energy source but also as a cost-effective solution to the electricity generation market. Various commercial solutions for grid-connected PV systems are available at any power level, ranging from multi-megawatt utility-scale solar farms to sub-kilowatt residential PV installations. Compared to utility-scale systems, the feasibility of small-scale residential PV installations is still limited by existing technologies that have not yet properly address issues like operation in weak grids, opaque and partial shading, etc. New market drivers such as warranty improvement to match the PV module lifespan, operation voltage range extension for application flexibility, and embedded energy storage for load shifting have again put small-scale PV systems in the spotlight. This Special Issue collects the latest developments in the field of power electronic converter topologies, control, design, and optimization for better energy yield, power conversion efficiency, reliability, and longer lifetime of the small-scale PV systems. This Special Issue will serve as a reference and update for academics, researchers, and practicing engineers to inspire new research and developments that pave the way for next-generation PV systems for residential and small commercial applications

Hybrid Amorphous-Selenium/CMOS Low-Light Imager

This thesis aims to demonstrate a low-light imager capable of moonlight-level imag- ing by combining a custom-designed complementary-metal-oxide-semiconductor (CMOS) pixel array with amorphous selenium (a-Se) as its photosensor. Because of the low dark current of a-Se compared to standard silicon photodiodes, this hybrid structure could enable imagers fabricated in standard mixed-signal CMOS processes to achieve low- light imaging. Such hybrid imagers could have low-light performances comparable to other low-light imagers fabricated in specialized CMOS image-sensor processes. The 320 (H) x 240 (V) imager contains four different pixel designs arranged in four quadrants, with pixel pitches of 7.76 μm x 7.76 μm in quadrants 1 to 3 and 7.76 μm x 8.66 μm in quadrant 4 (Q4). The different quadrants are built to examine various performance-enhancing circuit designs and techniques, including series-stacked devices for leakage suppression, charge-injection suppression that uses dummy transistors, and a programmable dual-capacity design for extended pixel dynamic range. The imager- performance parameters, such as noise, dynamic range, conversion gain, linearity, and full-well capacity were simulated and experimentally verified. This work will also de- scribe the external hardware and software designs used to operate the imager. This thesis summarizes and reports the overall electrical and optical performance of pixels in quadrant 1. The observed signal-to-noise ratio (SNR) of above 20 dB at an illuminance of 0.267 lux demonstrates that the imager can produce excellent images under moonlight-imaging conditions. This was achieved mainly through utilization of the long integration time enabled by circuit techniques implemented at the pixel level, as well as the low dark current of a-Se

High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology

High-Speed and Low-Energy On-Chip Communication Circuits.

Continuous technology scaling sharply reduces transistor delays, while fixed-length global wire delays have increased due to less wiring pitch with higher resistance and coupling capacitance. Due to this ever growing gap, long on-chip interconnects pose well-known latency, bandwidth, and energy challenges to high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, the increased complexity and high level of integration requires higher wire densities, worsening crosstalk noise and power consumption of conventionally repeated interconnects. Such increasing concerns in global on-chip wires motivate circuits to improve wire performance and energy while reducing the number of repeaters. This work presents circuit techniques and investigation for high-performance and energy-efficient on-chip communication in the aspects of encoding, data compression, self-timed current injection, signal pre-emphasis, low-swing signaling, and technology mapping. The improved bus designs also consider the constraints of robust operation and performance/energy gains across process corners and design space. Measurement results from 5mm links on 65nm and 90nm prototype chips validate 2.5-3X improvement in energy-delay product.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75800/1/jseo_1.pd