A Charge-Recycling Scheme and Ultra Low Voltage Self-Startup Charge Pump for Highly Energy Efficient Mixed Signal Systems-On-A-Chip

The advent of battery operated sensor-based electronic systems has provided a pressing need to design energy-efficient, ultra-low power integrated circuits as a means to improve the battery lifetime. This dissertation describes a scheme to lower the power requirement of a digital circuit through the use of charge-recycling and dynamic supply-voltage scaling techniques. The novel charge-recycling scheme proposed in this research demonstrates the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital design. The proposed scheme efficiently gathers the “ground-bound” charge into storage capacitor banks. This reclaimed charge is then subsequently recycled to power the source digital circuit. The charge-recycling methodology has been implemented on a 12-bit Gray-code counter operating at frequencies of less than 50 MHz. The circuit has been designed in a 90-nm process and measurement results reveal more than 41% reduction in the average energy consumption of the counter. The total energy savings including the power consumed for the generation of control signals aggregates to an average of 23%. The proposed methodology can be applied to an existing digital path without any design change to the circuit but with only small loss to the performance. Potential applications of this scheme are described, specifically in wide-temperature dynamic power reduction and as a source for energy harvesters. The second part of this dissertation deals with the design and development of a self-starting, ultra-low voltage, switched-capacitor (SC) DC-DC converter that is essential to an energy harvesting system. The proposed charge-pump based SC-converter operates from 125-mV input and thus enables battery-less operation in ultra-low voltage energy harvesters. The charge pump does not require any external components or expensive post-fabrication processing to enable low-voltage operation. This design has been implemented in a 130-nm CMOS process. While the proposed charge pump provides significant efficiency enhancement in energy harvesters, it can also be incorporated within charge recycling systems to facilitate adaptable charge-recycling levels. In total, this dissertation provides key components needed for highly energy-efficient mixed signal systems-on-a-chip

Design and Evaluation of High Power, High Efficiency and High Power Density Motor Drives for More Electric Aircrafts

More-electric aircraft (MEA) is an attractive concept as it can reduce carbon dioxide emission, relieve fossil-fuel consumption, improve the overall efficiency of aircraft, and reduce the operational costs. However, it poses substantial challenges in designing a high-performance motor drive system for such applications. In the report of Aircraft Technology Roadmap to 2050, the propulsion converter is required to be ultra-high efficiency, high power density, and high reliability. Though the wide band-gap devices, such as the Silicon-carbide based Metal Oxide Silicon Field Effect (SiC-MOSFET), shows better switching performance and improved high-temperature performance compared to the silicon counterparts, applying it to the MEA-related application is still challenging. The high switching speed of SiC-MOSFET reduces switching loss and enables the design of high-density converters. However, it poses intense challenges in limiting the stray inductance in the power stage. The fast switching behavior of SiC-MOSFET also challenges the design scalability by multi-chip parallel, which is essential in high-power-rating converters. Moreover, the partial discharge can happen at the lower voltage when the converter is operated at high altitude, low air-pressure conditions, which threatens the converter lifetime by the accelerated aging of the insulation system. This dissertation addresses these issues at the paper-design level, power-module level, and converter level, respectively. At the paper-design level, the proposed model-based design and optimization enables shoulder-by-shoulder performance comparison between different candidate topology and then generates optimal semiconductor design space for the selected topology. At the power-module level, this dissertation focuses on the development of an ultra-low inductance module by using a novel packaging structure that integrates the printed circuit board (PCB) with direct-bounding copper (DBC). The detailed power-loop optimization, thermal analysis, and fabrication guidance are discussed to demonstrate its performance and manufacturability. At the converter level, this dissertation provides a comprehensive design strategy to improve the performance of the laminated busbar. In the design of the busbar conduction layer, this work analyzed the impacts of each stray inductance item and then proposed a novel double-side decoupled conduction-layer structure with minimized stray inductance and improved dynamic current sharing. In the design of the insulation system of the busbar, this dissertation investigates the design strategy to ensure the busbar is free of partial discharge without sacrificing the parasitic control. Through the dissertation, a single-phase 150 kVA converter, a three-phase 450 kVA converter, and a 1.2 kV, 300 A power module are designed, fabricated, and tested to demonstrate the proposed design strategies

Design of a RF communication receiver front-end for ultra-low power and voltage applications in a FDSOI 28nm technology

The advances in the semiconductor and wireless industry have enabled the expansion of new paradigms, which have given rise to concepts like Internet of Things (IoT). Apart from qualities like size, speed or cost, the ever-increasing demand for autonomy focuses all design efforts in the minimization of power consumption. Scaling technologies and the request to reduce power consumption have pushed designers towards lower supply voltages. Despite the fact that technology scalability allows for faster transistors, radio-frequency (RF) integrated circuit (IC) design accuses the reduction of the voltage supply through frequency response degradation, which significantly deteriorates the overall performance. Analog and RF circuits in highend applications require substantial gate voltage overdrive to maintain device speed, which further complicates the design due to the reduction of voltage headroom. As a consequence, the necessity to develop circuit topologies capable to deal with low-power and low-voltage stringent constraints well suited to applications requiring long battery life and low cost emerges. This work aims to implement a low-noise amplifier and mixer stages of a radio-frequency receiver front-end working under an ultra-low power (< 100 ?W) and ultra-low voltage (< 0.8V) scenario while targeting decent overall performance. To cope with the stringent power requirements, 28nm FD-SOI technology will be used to take maximum profit of aggressive forward body bias and enhance transistor performance

Capacitor Optimization in Power Distribution Networks Using Numerical Computation Techniques

This paper presents a power distribution network (PDN) decoupling capacitor optimization application with three primary goals: reduction of solution times for large networks, development of flexible network scoring routines, and a concentration strictly on achieving the best network performance. Example optimizations are performed using broadband models of a printed circuit board (PCB), a chip-package, on-die networks, and candidate capacitors. A novel worst-case time-domain optimization technique is presented as an alternative to the traditional frequency-domain approach. The trade-offs and criteria for scoring the computed network are presented. The output is a recommended set of capacitors which can then be applied to the product design.Comment: 24 pages, 13 figures, DesignCon 202

Understanding and Countermeasures against IoT Physical Side Channel Leakage

With the proliferation of cheap bulk SSD storage and better batteries in the last few years we are experiencing an explosion in the number of Internet of Things (IoT) devices flooding the market, smartphone connected point-of-sale devices (e.g. Square), home monitoring devices (e.g. NEST), fitness monitoring devices (e.g. Fitbit), and smart-watches. With new IoT devices come new security threats that have yet to be adequately evaluated. We propose uLeech, a new embedded trusted platform module for next-generation power scavenging devices. Such power scavenging devices are already widely deployed. For instance, the Square point-of-sale reader uses the microphone/speaker interface of a smartphone for communications and as a power supply. Such devices are being used as trusted devices in security-critical applications, without having been adequately evaluated. uLeech can securely store keys and provide cryptographic services to any connected smartphone. Our design also facilitates physical side-channel security analysis by providing interfaces to facilitate the acquisition of power traces and clock manipulation attacks. Thus uLeech empowers security researchers to analyze leakage in next- generation embedded and IoT devices and to evaluate countermeasures before deployment. Even the most secure systems reveal their secrets through secret-dependent computation. Secret- dependent computation is detectable by monitoring a system’s time, power, or outputs. Common defenses to side-channel emanations include adding noise to the channel or making algorithmic changes to mitigate specific side-channels. Unfortunately, existing solutions are not automatic, not comprehensive, or not practical. We propose an isolation-based approach for eliminating power and timing side-channels that is automatic, comprehensive, and practical. Our approach eliminates side-channels by leveraging integrated decoupling capacitors to electrically isolate trusted computation from the adversary. Software has the ability to request a fixed- power/time quantum of isolated computation. By discretizing power and time, our approach controls the granularity of side-channel leakage; the only burden on programmers is to ensure that all secret-dependent execution differences converge within a power/time quantum. We design and implement three approaches to power/time-based quantization and isolation: a wholly-digital version, a hybrid version that uses capacitors for time tracking, and a full- custom version. We evaluate the overheads of our proposed controllers with respect to software implementations of AES and RSA running on an ARM- based microcontroller and hardware implementations AES and RSA using a 22nm process technology. We also validate the effectiveness and real-world efficiency of our approach by building a prototype consisting of an ARM microcontroller, an FPGA, and discrete circuit components. Lastly, we examine the root cause of Electromagnetic (EM) side-channel attacks on Integrated Circuits (ICs) to augment the Quantized Computing design to mitigate EM leakage. By leveraging the isolation nature of our Quantized Computing design, we can effectively reduce the length and power of the unintended EM antennas created by the wire layers in an IC

Ultra-Low Power Circuit Design for Miniaturized IoT Platform

This thesis examines the ultra-low power circuit techniques for mm-scale Internet of Things (IoT) platforms. The IoT devices are known for their small form factors and limited battery capacity and lifespan. So, ultra-low power consumption of always-on blocks is required for the IoT devices that adopt aggressive duty-cycling for high power efficiency and long lifespan. Several problems need to be addressed regarding IoT device designs, such as ultra-low power circuit design techniques for sleep mode and energy-efficient and fast data rate transmission for active mode communication. Therefore, this thesis highlights the ultra-low power always-on systems, focusing on energy efficient optical transmission in order to miniaturize the IoT systems. First, this thesis presents a battery-less sub-nW micro-controller for an always-operating system implemented with a newly proposed logic family. Second, it proposes an always-operating sub-nW light-to-digital converter to measure instant light intensity and cumulative light exposure, which employs the characteristics of this proposed logic family. Third, it presents an ultra-low standby power optical wake-up receiver with ambient light canceling using dual-mode operation. Finally, an energy-efficient low power optical transmitter for an implantable IoT device is suggested. Implications for future research are also provided.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/145862/1/imhotep_1.pd

Boost Matrix Converters in Clean Energy Systems

This dissertation describes an investigation of novel power electronic converters, based on the ultra-sparse matrix topology and characterized by the minimum number of semiconductor switches. The Z-source, Quasi Z-source, Series Z-source and Switched-inductor Z-source networks were originally proposed for boosting the output voltage of power electronic inverters. These ideas were extended here on three-phase to three-phase and three-phase to single-phase indirect matrix converters. For the three-phase to three-phase matrix converters, the Z-source networks are placed between the three-switch input rectifier stage and the output six-switch inverter stage. A brief shoot-through state produces the voltage boost. An optimal pulse width modulation technique was developed to achieve high boosting capability and minimum switching losses in the converter. For the three-phase to single-phase matrix converters, those networks are placed similarly. For control purposes, a new modulation technique has been developed. As an example application, the proposed converters constitute a viable alternative to the existing solutions in residential wind-energy systems, where a low-voltage variable-speed generator feeds power to the higher-voltage fixed-frequency grid.Comprehensive analytical derivations and simulation results were carried out to investigate the operation of the proposed converters. Performance of the proposed converters was then compared between each other as well as with conventional converters. The operation of the converters was experimentally validated using a laboratory prototype

Vibration energy harvesters for wireless sensor networks for aircraft health monitoring

Traditional power supply for wireless sensor nodes is batteries. However, the application of batteries in WSN has been limited due to their large size, low capacity, limited working life, and replacement cost. With rapid advancements in microelectronics, power consumption of WSN is getting lower and hence the energy harvested from ambient may be sufficient to power the tiny sensor nodes and eliminate batteries completely. As vibration is the widespread ambient source that exists in abundance on an aircraft, a WSN node system used for aircraft health monitoring powered by a piezoelectric energy harvester was designed and manufactured. Furthermore, simulations were performed to validate the design and evaluate the performance. In addition, the Z-Stack protocol was migrated to run on the system and initial experiments were carried out to analyse the current consumption of the system. A new approach for power management was reported, the execution of the operations were determined by the amount of the energy stored on the capacitor. A novel power saving interface was also developed to minimise the power consumption during the voltage measurement