Towards a hardware-assisted information flow tracking ecosystem for ARM processors

International audienceThis work details a hardware-assisted approach for information flow tracking implemented on reconfigurable chips. Current solutions are either time-consuming or hardly portable (modifications of both software/hardware layers). This work takes benefits from debug components included in ARMv7 processors to retrieve details on instructions committed by the CPU. First results in terms of silicon area and time overheads are also given

HardBlare: a Hardware-Assisted Approach for Dynamic Information Flow Tracking

International audienceThe HardBlare project proposes a software/hardware co-design methodology to ensure that security properties are preserved all along the execution of the system but also during files storage. Based on the Dynamic Information Flow Tracking (DIFT) that generally consists in attaching tags to denote the type of information that are saved or generated within the system. These tags are then propagated when the system evolves and information flow control is performed in order to guarantee the safe execution and storage within the system monitored by security policies

Predictive Warning System for a Class of Shared-Control Vehicular CPS via Dynamic Information Flow Tracking.

Manned vehicles are maturing into robotics agents under shared control. Vehicle op- erators will be confronted with understanding the expected response from the robotic agent to their actions. I propose a warning system framework to continuously track human inputs, identify possible conflicts and provide contextual warning information to the operator to help avoid accidents. I consider a robotic agent which nominal operation can be encoded using the hybrid automata framework with human inputs. Trajectory prediction methods are used to identify possible conflicts, coded as the avoid set of the system. Using Dynamic Information Flow Tracking (DIFT), human inputs and their effect over time are accumulated and classified in a continuous range between spurious or legitimate inputs

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis

High-level synthesis (HLS) tools have made significant progress in the past few years, improving the design productivity for hardware accelerators and becoming mainstream in industry to create specialized system-on-chip architectures. Increasing the level of security of these heterogeneous architectures is becoming critical. However, state-of-the-art security countermeasures are still applied only to the code executing on the processor cores or manually implemented into the generated components, leading to suboptimal and sometimes even insecure designs. This letter discusses extensions to HLS tools for creating secure heterogeneous architectures