OPTIMAL AREA AND PERFORMANCE MAPPING OF K-LUT BASED FPGAS

FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an arbitrary, given wide, function can be implemented by a programmable logic block, unfortunately, it is generally, a very difficult problem. This problem is called the Boolean matching problem. This paper introduces a new implemented algorithm able to map, both for area and performance, combinational networks using k-LUT based FPGAs.k-LUT based FPGAs, combinational circuits, performance-driven mapping.

The Design of Cube Calculus Machine Using Sram-Based Fpga Reconfigurable Hardware Dec’s Perle-1 Board

Presented in this thesis are new approaches to column compatibility checking and column-based input/output encoding for Curtis decompositions of switching functions. These approaches can be used in Curtis-type functional decomposition programs for applications in several scientific disciplines. Examples of applications are: minimization of combinational and sequential logic) mapping of logic functions to programmable logic devices such as CPLDs, MPGAs, and FPGAs, data encryption, data compression, pattern recognition) and image refinement. Presently, Curtis-type functional decomposition programs are used primarily for experimental purposes due to performance, quality, and compatibility issues. However) in the past few years a renewal of interest in the area of functional decomposition has resulted in significant improvements in performance and quality of multi-level decomposition programs. The goal of this thesis is to introduce algorithms that can significantly improve the performance and quality of Curtis-type decomposition programs. In doing so, it is hoped that a Curtis-type decomposition program, complete with efficient, high quality algorithms for decomposition, will be a feasible tool for use in one or more practical applications. Various testing and analyses were performed in order to evaluate the potential of algorithms presented in this thesis for use in a high quality Curtis-type decomposition program. Testing was done using a binary input, binary output Curtis-type decomposition program MULTIS/GUD. This program was implemented here at Portland State University by the Portland Oregon Logic Optimization Group

SMTBDD: New Form of BDD for Logic Synthesis

The main purpose of the paper is to suggest a new form of BDD – SMTBDD diagram, methods of obtaining, and its basic features. The idea of using SMTBDD diagram in the process of logic synthesis dedicated to FPGA structures is presented. The creation of SMTBDD diagrams is the result of cutting BDD diagram which is the effect of multiple decomposition. The essence of a proposed decomposition method rests on the way of determining the number of necessary ‘g’ bounded functions on the basis of the content of a root table connected with an appropriate SMTBDD diagram. The article presents the methods of searching non-disjoint decomposition using SMTBDD diagrams. Besides, it analyzes the techniques of choosing cutting levels as far as effective technology mapping is concerned. The paper also discusses the results of the experiments which confirm the efficiency of the analyzed decomposition methods

Digital Beamforming Implementation on an FPGA Platform

This work is part of UPC contribution to the CORPA (Cost-Optimised high Performance Active Receive Phase Array antenna for mobile terminals) project of ESA (European Space Agency)The objective of the work presented is to implement a Digital Beamforming (DBF) platform for an antenna array receiver designed for the S-DMB system. Our project deals with the design of antenna arrays from a hardware point of view, in contrast to other theo- retic studies regarding DBF algorithms. Hence, we will study practical aspects of DBF implementation such as signal quantization and required computational resources

Computing Performance Benchmarks among CPU, GPU, and FPGA

In recent years, the world of high performance computing has been developing rapidly. The goal of this project was to conduct computing performance benchmarks on three major computing platforms, CPUs, GPUs, and FPGAs. A total of 66 benchmarks were evaluated. GPUs outperformed the other platforms in terms of execution time. CPUs outperformed in overall execution combined with transfer time. FPGAs outperformed for fixed algorithms using streaming. The team made several recommendations for further research in this area

Minimize Logic Synthesis FPGA – Extraction And Substitution Problems

The objective of multi-level logic synthesis of FPGA is to find the “best” multi-level structure, where “best” in this case means an equivalent presentation that is optimal with respect to various parameters such as size, speed or power consumption... Five basic operations are used in order to reach this goal: decomposition, extraction, factoring, substitution and collapsing. In this paper we propose a novel application of Walsh spectral transformation to the evaluation of Boolean function correlation. In particular, we present an algorithm with approach to solve the problems of extraction and substitution based on the use of Walsh spectral presentation. The method, operating in the transform domain, has appeared to be more advantageous than traditional approaches, using operations in the Boolean domain, concerning both memory occupation and execution time on some classes of functions

Overview on Strategies and Approaches for FPGA Programming

This paper presents an overview of strategies and approaches for FPGA programming. At first, design entry methods are briefly introduced. Then, the concepts of FPGA programming in some perspective viewpoints, such as: execution perspective, modelling perspective, programming style perspective, construction methodology perspective and synthesis perspective will be explained. Finally, the principle of VHDL programming use synchronization-evolution-action approach is introduced

Development of Graphical Analytical Models for Digital Signal Processing System Structures

This paper proposes an improved method for describing digital filter structures as part of digital signal processing (DSP) systems, characterized by the high information content of its models. The proposed approach is used to perform the synthesis of graphical analytical models of DSP systems as well as their analysis by means of multilevel decomposition. All the system elements are presented in the form of functional structures, and the input counts processing - by the discrete system - is considered as the process of converting arguments by these functional structures. Moreover, graphical analytical models of basic structures of the finite impulse response (FIR) and infinite impulse response (IIR) filters are developed and integrated with an object-oriented programming language to be used in various projects in the form of snap-in modules. Additionally, the method, proposed in this paper is used for synthesising an optimized structure of a digital filter for calculating the mean and current values of the determined periodic signal at the optimal discrete system’s speed and invariance to discretization frequency. The obtained practical results show that the proposed method can be used with great confidence in synthesizing optimized structures of digital filters as well as in the optimization of DSP systems’ structures with the purpose of identifying the mean and RMS voltage values. The latter is an indicator that the proposed method can be applied to various electronic systems

Implementation of a Real-Time Beamforming System on Field Programmable Gate Array

Beamforming is an important technique in array signal processing and wireless communication systems. In this project, we investigate the Minimum Variance Distortionless Response (MVDR) beamforming technique and its implementation. The QR-RLS algorithm is chosen because of its advantages of numerical stability and systolic array architecture. The team successfully implemented the real-time beamforming of a linear array with 3 receiving antennas on a Xilinx Virtex-5 FPGA platform. Both the simulation and hardware implementation results are presented in this report