103 research outputs found

    Planar graph coloring avoiding monochromatic subgraphs: trees and paths make things difficult

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    We consider the problem of coloring a planar graph with the minimum number of colors such that each color class avoids one or more forbidden graphs as subgraphs. We perform a detailed study of the computational complexity of this problem

    The square of a planar cubic graph is 77-colorable

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    We prove the conjecture made by G.Wegner in 1977 that the square of every planar, cubic graph is 77-colorable. Here, 77 cannot be replaced by 66

    On star edge colorings of bipartite and subcubic graphs

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    A star edge coloring of a graph is a proper edge coloring with no 22-colored path or cycle of length four. The star chromatic index χst′(G)\chi'_{st}(G) of GG is the minimum number tt for which GG has a star edge coloring with tt colors. We prove upper bounds for the star chromatic index of complete bipartite graphs; in particular we obtain tight upper bounds for the case when one part has size at most 33. We also consider bipartite graphs GG where all vertices in one part have maximum degree 22 and all vertices in the other part has maximum degree bb. Let kk be an integer (k≥1k\geq 1), we prove that if b=2k+1b=2k+1 then χst′(G)≤3k+2\chi'_{st}(G) \leq 3k+2; and if b=2kb=2k, then χst′(G)≤3k\chi'_{st}(G) \leq 3k; both upper bounds are sharp. Finally, we consider the well-known conjecture that subcubic graphs have star chromatic index at most 66; in particular we settle this conjecture for cubic Halin graphs.Comment: 18 page

    Planar graph coloring avoiding monochromatic subgraphs : trees and paths make it difficult

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    We consider the problem of coloring a planar graph with the minimum number of colors so that each color class avoids one or more forbidden graphs as subgraphs. We perform a detailed study of the computational complexity of this problem. We present a complete picture for the case with a single forbidden connected (induced or noninduced) subgraph. The 2-coloring problem is NP-hard if the forbidden subgraph is a tree with at least two edges, and it is polynomially solvable in all other cases. The 3-coloring problem is NP-hard if the forbidden subgraph is a path with at least one edge, and it is polynomially solvable in all other cases. We also derive results for several forbidden sets of cycles. In particular, we prove that it is NP-complete to decide if a planar graph can be 2-colored so that no cycle of length at most 5 is monochromatic

    VLSI Routing for Advanced Technology

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    Routing is a major step in VLSI design, the design process of complex integrated circuits (commonly known as chips). The basic task in routing is to connect predetermined locations on a chip (pins) with wires which serve as electrical connections. One main challenge in routing for advanced chip technology is the increasing complexity of design rules which reflect manufacturing requirements. In this thesis we investigate various aspects of this challenge. First, we consider polygon decomposition problems in the context of VLSI design rules. We introduce different width notions for polygons which are important for width-dependent design rules in VLSI routing, and we present efficient algorithms for computing width-preserving decompositions of rectilinear polygons into rectangles. Such decompositions are used in routing to allow for fast design rule checking. A main contribution of this thesis is an O(n) time algorithm for computing a decomposition of a simple rectilinear polygon with n vertices into O(n) rectangles, preseverving two-dimensional width. Here the two-dimensional width at a point of the polygon is defined as the edge length of a largest square that contains the point and is contained in the polygon. In order to obtain these results we establish a connection between such decompositions and Voronoi diagrams. Furthermore, we consider implications of multiple patterning and other advanced design rules for VLSI routing. The main contribution in this context is the detailed description of a routing approach which is able to manage such advanced design rules. As a main algorithmic concept we use multi-label shortest paths where certain path properties (which model design rules) can be enforced by defining labels assigned to path vertices and allowing only certain label transitions. The described approach has been implemented in BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics, University of Bonn, in cooperation with IBM. We present experimental results confirming that a flow combining BonnRoute and an external cleanup step produces far superior results compared to an industry standard router. In particular, our proposed flow runs more than twice as fast, reduces the via count by more than 20%, the wiring length by more than 10%, and the number of remaining design rule errors by more than 60%. These results obtained by applying our multiple patterning approach to real-world chip instances provided by IBM are another main contribution of this thesis. We note that IBM uses our proposed combined BonnRoute flow as the default tool for signal routing
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