AREA AND POWER-EFFICIENT RECONFIGURABLE DIGITAL DOWN CONVERTER ON FPGA

This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output

A survey on OFDM-based elastic core optical networking

Orthogonal frequency-division multiplexing (OFDM) is a modulation technology that has been widely adopted in many new and emerging broadband wireless and wireline communication systems. Due to its capability to transmit a high-speed data stream using multiple spectral-overlapped lower-speed subcarriers, OFDM technology offers superior advantages of high spectrum efficiency, robustness against inter-carrier and inter-symbol interference, adaptability to server channel conditions, etc. In recent years, there have been intensive studies on optical OFDM (O-OFDM) transmission technologies, and it is considered a promising technology for future ultra-high-speed optical transmission. Based on O-OFDM technology, a novel elastic optical network architecture with immense flexibility and scalability in spectrum allocation and data rate accommodation could be built to support diverse services and the rapid growth of Internet traffic in the future. In this paper, we present a comprehensive survey on OFDM-based elastic optical network technologies, including basic principles of OFDM, O-OFDM technologies, the architectures of OFDM-based elastic core optical networks, and related key enabling technologies. The main advantages and issues of OFDM-based elastic core optical networks that are under research are also discussed

Using Quantum Computers for Quantum Simulation

Numerical simulation of quantum systems is crucial to further our understanding of natural phenomena. Many systems of key interest and importance, in areas such as superconducting materials and quantum chemistry, are thought to be described by models which we cannot solve with sufficient accuracy, neither analytically nor numerically with classical computers. Using a quantum computer to simulate such quantum systems has been viewed as a key application of quantum computation from the very beginning of the field in the 1980s. Moreover, useful results beyond the reach of classical computation are expected to be accessible with fewer than a hundred qubits, making quantum simulation potentially one of the earliest practical applications of quantum computers. In this paper we survey the theoretical and experimental development of quantum simulation using quantum computers, from the first ideas to the intense research efforts currently underway.Comment: 43 pages, 136 references, review article, v2 major revisions in response to referee comments, v3 significant revisions, identical to published version apart from format, ArXiv version has table of contents and references in alphabetical orde

An Optoelectronic Stimulator for Retinal Prosthesis

Retinal prostheses require the presence of viable population of cells in the inner retina. Evaluations of retina with Age-Related Macular Degeneration (AMD) and Retinitis Pigmentosa (RP) have shown a large number of cells remain in the inner retina compared with the outer retina. Therefore, vision loss caused by AMD and RP is potentially treatable with retinal prostheses. Photostimulation based retinal prostheses have shown many advantages compared with retinal implants. In contrary to electrode based stimulation, light does not require mechanical contact. Therefore, the system can be completely external and not does have the power and degradation problems of implanted devices. In addition, the stimulating point is flexible and does not require a prior decision on the stimulation location. Furthermore, a beam of light can be projected on tissue with both temporal and spatial precision. This thesis aims at fi nding a feasible solution to such a system. Firstly, a prototype of an optoelectronic stimulator was proposed and implemented by using the Xilinx Virtex-4 FPGA evaluation board. The platform was used to demonstrate the possibility of photostimulation of the photosensitized neurons. Meanwhile, with the aim of developing a portable retinal prosthesis, a system on chip (SoC) architecture was proposed and a wide tuning range sinusoidal voltage-controlled oscillator (VCO) which is the pivotal component of the system was designed. The VCO is based on a new designed Complementary Metal Oxide Semiconductor (CMOS) Operational Transconductance Ampli er (OTA) which achieves a good linearity over a wide tuning range. Both the OTA and the VCO were fabricated in the AMS 0.35 µm CMOS process. Finally a 9X9 CMOS image sensor with spiking pixels was designed. Each pixel acts as an independent oscillator whose frequency is controlled by the incident light intensity. The sensor was fabricated in the AMS 0.35 µm CMOS Opto Process. Experimental validation and measured results are provided

NASA SBIR abstracts of 1991 phase 1 projects

The objectives of 301 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1991 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 301, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1991 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included

NASA patent abstracts bibliography: A continuing bibliography. Section 1: Abstracts (supplement 38)

Abstracts are provided for 132 patents and patent applications entered into the NASA scientific and technical information system during the period July 1990 through December 1990. Each entry consists of a citation, an abstract, and in most cases, a key illustration selected from the patent or patent application

Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks

Quantum information processing with tunable and low-loss superconducting circuits

The perhaps most promising platform for quantum information processing is the circuit-QED architecture based on superconducting circuits representing quantum bits. These circuits must be made with low losses so that the quantum information is retained for as long as possible. We developed fabrication processes achieving state-of-the-art coherence times of over 100 \ub5s. We identified the primary source of loss to be parasitic two-level systems by studying fluctuations of qubit relaxation times.Using our high-coherence circuits, we implemented a quantum processor built on fixed-frequency qubits and frequency-tunable couplers. The tunable couplers were lumped-element LC resonators, where the inductance came from a superconducting quantum interference device (SQUID). We achieved a controlled-phase gate with a fidelity of 99% by parametric modulation of the coupler frequency. Using this device, and another similar to it, we demonstrated two different quantum algorithms, the quantum approximate optimization algorithm, and density matrix exponentiation. We achieved high algorithmic fidelities, aided by our carefully calibrated gates.Additionally, we researched parametric oscillations using frequency-tunable resonators. Previously, degenerate parametric oscillations have been demonstrated by modulation of the resonant frequency at twice that frequency. We use this phenomenon to implement a readout method for a superconducting qubit with a fidelity of 98.7%. We demonstrated correlated radiation in nondegenerate parametric oscillations by modulating at the sum of two resonant frequencies of a multimode resonator. We showed an excellent quantitative agreement between the classical properties of the oscillations with a theoretical model. Moreover, we studied higher-order modulation at up to five times their resonant frequencies. These types of parametric oscillation states might be used as a quantum resource for continuous-variable quantum computing

Computing 256-bit Elliptic Curve Logarithm in 9 Hours with 126133 Cat Qubits

Cat qubits provide appealing building blocks for quantum computing. They exhibit a tunable noise bias yielding an exponential suppression of bit-flips with the average photon number and a protection against the remaining phase errors can be ensured by a simple repetition code. We here quantify the cost of a repetition code and provide a valuable guidance for the choice of a large scale architecture using cat qubits by realizing a performance analysis based on the computation of discrete logarithms on an elliptic curve with Shor's algorithm. By focusing on a 2D grid of cat qubits with neighboring connectivity, we propose to implement two-qubit gates via lattice surgery and Toffoli gates with off-line fault-tolerant preparation of magic states through projective measurements and subsequent gate teleportations. All-to-all connectivity between logical qubits is ensured by routing qubits. Assuming a ratio between single-photon and two-photon losses of $10^{-5}$ and a cycle time of 500 nanoseconds, we show concretely that such an architecture can compute $256$-bit elliptic curve logarithm in $9$ hours with 126133 cat qubits. We give the details of the realization of Shor's algorithm so that the proposed performance analysis can be easily reused to guide the choice of architecture for others platforms.Comment: 4+34 pages, 32 figures, 5 table

Computing With Hybrid Material Oscillators

The evolution of computers is driven by advances not only in computer science, but also in materials science. As the post-CMOS era approaches, research is increasingly focusing on flexible and unconventional computing systems, including the study of systems that incorporate new computational paradigms into the materials, enabling the computer and the material to be the same entity. In this dissertation, we design a coupled oscillator system based on a new hybrid material that can autonomously transduce chemical, mechanical, and electrical energy. Each material unit in this system integrates a self-oscillating gel, which undergoes the Belousov-Zhabotinsky (BZ) reaction, with an overlaying piezoelectric (PZ) cantilever. The chemo-mechanical oscillations of the BZ gels deflect the piezoelectric layer, which consequently generates a voltage across the material. When these BZ-PZ units are connected in series by electrical wires, the oscillations of these coupled units become synchronized across the network, with the mode of synchronization depending on the polarity of the piezoelectric. Taking advantage of this synchronization behavior, we demonstrate that the network of coupled BZ-PZ oscillators can perform specific computational tasks such as pattern matching in a self-organized manner, without external electrical power sources. The results of the computational modeling show that the convergence time for stable synchronization gives a distance measure between the “stored” and “input” patterns, which are encoded by the connection and phases of BZ-PZ oscillators. In addition, we demonstrate two methods to enrich the information representation in our system. One is to employ multiple BZ-PZ oscillator networks in parallel and to process information encoded in different channels. The other is to introduce capacitors into a BZ-PZ network that modify the dynamical behavior of the systems and increase the information storage. We analyze and simulate the proposed coupled oscillator systems by using linear stability analysis and phase models and explore their potential computational capabilities. Through these studies, we establish experimentally realizable design rules for creating “materials that compute”