Syndrome decoding of Reed-Muller codes and tensor decomposition over finite fields

Reed-Muller codes are some of the oldest and most widely studied error-correcting codes, of interest for both their algebraic structure as well as their many algorithmic properties. A recent beautiful result of Saptharishi, Shpilka and Volk showed that for binary Reed-Muller codes of length $n$ and distance $d = O(1)$, one can correct $\operatorname{polylog}(n)$ random errors in $\operatorname{poly}(n)$ time (which is well beyond the worst-case error tolerance of $O(1)$). In this paper, we consider the problem of `syndrome decoding' Reed-Muller codes from random errors. More specifically, given the $\operatorname{polylog}(n)$-bit long syndrome vector of a codeword corrupted in $\operatorname{polylog}(n)$ random coordinates, we would like to compute the locations of the codeword corruptions. This problem turns out to be equivalent to a basic question about computing tensor decomposition of random low-rank tensors over finite fields. Our main result is that syndrome decoding of Reed-Muller codes (and the equivalent tensor decomposition problem) can be solved efficiently, i.e., in $\operatorname{polylog}(n)$ time. We give two algorithms for this problem: 1. The first algorithm is a finite field variant of a classical algorithm for tensor decomposition over real numbers due to Jennrich. This also gives an alternate proof for the main result of Saptharishi et al. 2. The second algorithm is obtained by implementing the steps of the Berlekamp-Welch-style decoding algorithm of Saptharishi et al. in sublinear-time. The main new ingredient is an algorithm for solving certain kinds of systems of polynomial equations.Comment: 24 page

A Reconfigurable Butterfly Architecture for Fourier and Fermat Transforms

International audienceReconfiguration is an essential part of Soft- Ware Radio (SWR) technology. Thanks to this technique, systems are designed for change in operating mode with the aim to carry out several types of computations. In this SWR context, the Fast Fourier Transform (FFT) operator was defined as a common operator for many classical telecommunications operations [1]. In this paper we propose a new architecture for this operator that makes it a device intended to perform two different transforms. The first one is the Fast Fourier Transform (FFT) used for the classical operations in the complex field. The second one is the Fermat Number Transform (FNT) in the Galois Field (GF) for channel coding and decoding

Spike processing model of the brain

The timing of a spike within a specific time period is used to identify a place in space (input terminal) and/or sense changes in energy or position in the environment, and is used to determine the motion of an actuator or the activation of a place in space (output terminal). The timing of a spike is specified by a sensor or a time delay memory cell that is preset (predetermined) or set through experience (empirical). Time delay memory cells are arranged in decoding networks that activate specific output terminals based upon the timing of incoming spike trains, or arranged in encoding networks that generate spike trains from activated input terminals. These spike trains form semi-axes that can transmit large quantities of information in one direction through a single conductor, and are essential in the transmission of information from peripheral neurons to and from the brain through the spinal chord

Decoding billions of integers per second through vectorization

In many important applications -- such as search engines and relational database systems -- data is stored in the form of arrays of integers. Encoding and, most importantly, decoding of these arrays consumes considerable CPU time. Therefore, substantial effort has been made to reduce costs associated with compression and decompression. In particular, researchers have exploited the superscalar nature of modern processors and SIMD instructions. Nevertheless, we introduce a novel vectorized scheme called SIMD-BP128 that improves over previously proposed vectorized approaches. It is nearly twice as fast as the previously fastest schemes on desktop processors (varint-G8IU and PFOR). At the same time, SIMD-BP128 saves up to 2 bits per integer. For even better compression, we propose another new vectorized scheme (SIMD-FastPFOR) that has a compression ratio within 10% of a state-of-the-art scheme (Simple-8b) while being two times faster during decoding.Comment: For software, see https://github.com/lemire/FastPFor, For data, see http://boytsov.info/datasets/clueweb09gap