High‐Speed Deterministic‐Latency Serial IO

In digital systems, serial IO at speeds in the range from 1 to 20 Gbps is realized by means of dedicated transceivers, named serializer-deserializers (SerDeses). In general, due to their internal architecture, the data transfer delay, or the latency, may vary after a reset of the device. On the other hand, some applications, such as high-speed transfer protocols for analog-to-digital and digital-to-analog converters, trigger and data acquisition systems, clock distribution, synchronization and control of radio equipment need this delay to be constant at each reset. In this chapter, we focus on a serial IO architecture based on configurable transceivers embedded in field-programmable gate arrays (FPGAs). We will show how it is possible to achieve deterministic-latency operation in a line-code-independent way. As a case study, we will consider a synchronous 2.5-Gbps serial link based on an 8b10b line code

Development of a field-deployable error rate tester for 10 Gbps fiber optic transmission utilizing field programmable gate array technology

The bit error rate of a digital signal is the number of bits received incorrectly divided by the total number of bits received. A Bit Error Rate Tester (BERT) is a piece of equipment designed to calculate the bit error rate of a communication medium. The typical method of bit error rate testing is to produce a pseudorandom-binary sequence that can be transmitted over a fiber optic line and verified on the receiving end. The current equipment for bit error rate testing of 10 Gbps fiber optic data equipment is generally large, labbench-based equipment which is not feasible for use in the field. Utilizing current FPGA technology, the design, and the manufacture of BERT equipment for 10 Gbps fiber optic data lines that is compact enough for field use should be feasible. This thesis investigates prevailing methods for bit error testing and compares them for relative strengths and weaknesses. Based on this analysis, a proposed process will allow BERT implementation in a compact package. Successful development and implementation of this design will facilitate the productization of a portable and cheaper alternative to the more expensive and stationary desktop BERTs in current use

Digital Serializer Design for a SerDes Chip in 130nm CMOS Technology

The development of this project is derived from the effort of previous generations from the System on Chip Design Specialty Program at ITESO, who have pioneered the creation of a serializer-deserializer device for high-speed communications in CMOS technology, aiming towards a small and efficient device. The design flow and enhancements implemented within the digital serializer module of the SerDes system, consists of an 8b10b encoder followed by a parallel to serial converter that together reaches a maximum frequency of 239 MHz in a typical cmrf8sf (130 nm) technology manufacturing process, implemented with Cadence tools. The rtl and testbench were taken from the work of Efrain Arrambide, adding a register to store the current disparity value, and thus, enhance the code by adding primitive blocks to improve the behavior of the serializer module and the validation process, generating a summary for every run. The system on chip flow is followed by choosing the variables that best fit the design and a layout with no design violations is generated during the physical synthesis. The individual module layouts were completed successfully in terms of behavior and violations, while the integration of the mixed signal device showed errors that were not resolved in time for manufacturing.El desarrollo de este proyecto parte del trabajo realizado por las generaciones anteriores de la especialidad de diseño de circuitos integrados del ITESO, quienes fueron pioneros en la creación de un dispositivo para comunicaciones de alta velocidad en tecnología CMOS, con el objetivo de obtener un producto final pequeño y eficiente. El flujo de diseño y mejoras implementadas al módulo serializador digital del sistema SerDes, el cual consiste en un codificador 8b10b seguido de un convertidor de datos de paralelo a serial, alcanza una frecuencia máxima de 239 MHz al ser fabricado y operado en condiciones típicas con la tecnología cmrf8sf (130 nm), además de ser implementado con las herramientas proveídas por Cadence. El código de descripción de hardware y banco de pruebas fueron tomados originalmente de los entregados por Efrain Arrambide, a lo que se le agregó un registro para almacenar el valor de la disparidad del dato enviado, así como la adición de bloques básicos para mejorar el comportamiento y se simplificó el código Verilog. El proceso de validación fue mejorado de tal manera que se prueban bloques por separado y cada iteración genera un registro de transacciones y un resumen al final con los resultados de manera automática para cada iteración. El flujo del diseño de sistemas en chip fue seguido por completo, eligiendo las variables que mejor se adaptan a la respuesta y especificaciones del sistema, así como buscar que genere ninguna violación en el diseño físico. Los distintos bloques del sistema serializador-deserializador fueron diseñados y verificados con éxito, sin embargo, la integración del sistema de señal mixta no fue completada debido a errores que no se lograron resolver a tiempo para cumplir con la fecha de fabricación.ITESO, A. C.Consejo Nacional de Ciencia y Tecnologí

MULTI‐FLEX PROTOTYPE FOR THE LAYER 2 ATLAS ALPINE STAVES LAYOUT

LAPP is involved in the phaseII upgrade for the ATLAS pixels tracker [1]. The LAPP’s group is currently designing a pixels detector layout called Alpine Staves. This layout should allow to savematter in the detector. The silicon detectors should also cover a very high angle in the forward region.The pixel modules data transmission is an issue because of the very high number of channels and because of the high data rates. A first study in 2014 allowed to estimate the feasibility of data transmission and powering of the pixel modules along the staves thanks to multicore flexes. Discussions with manufactures have showed that the multicore solution is too complex in term of feasibility and cost. A simpler solution is a multiple flex made of several double‐sided cores. This study presents the methods and principles for a transmission flex based on the Alpine layout but results can be applied to a general stave‐based layout. A prototype has been produced in 2015 and test results show thecapabilities of a flex designed with real detector specifications

High-speed data transfer with FPGAs and QSFP+ modules

We present test results and characterization of a data transmission system based on a last generation FPGA and a commercial QSFP+ (Quad Small Form Pluggable +) module. QSFP+ standard defines a hot-pluggable transceiver available in copper or optical cable assemblies for an aggregated bandwidth of up to 40 Gbps. We implemented a complete testbench based on a commercial development card mounting an Altera Stratix IV FPGA with 24 serial transceivers at 8.5 Gbps, together with a custom mezzanine hosting three QSFP+ modules. We present test results and signal integrity measurements up to an aggregated bandwidth of 12 Gbps.Comment: 5 pages, 3 figures, Published on JINST Journal of Instrumentation proceedings of Topical Workshop on Electronics for Particle Physics 2010, 20-24 September 2010, Aachen, Germany(R Ammendola et al 2010 JINST 5 C12019

A point-to-point link for data, trigger, clock and control over copper or fibre

Upgrades of the LHC detectors target significantly higher event rates and higher bandwidth over point-to-point links. The Data, Trigger, Clock and Control (DTCC) is a new custom link protocol for data and control streams over different physical media, as copper or optical fibre. The DTCC link is implemented over 8b10b encoding. A version of the DTCC link over standard Category 6 cables is planned to be used with ALICE EMCal Calorimeters after its LS1 upgrade with a significant increase of the readout rate.Tarazona Martínez, A.; Gnanvo, K.; Martoiu, S.; Muller, H.; Toledo Alarcón, JF. (2014). A point-to-point link for data, trigger, clock and control over copper or fibre. Journal of Instrumentation. 9:1-12. doi:10.1088/1748-0221/9/06/T06004S1129Zhang, F., Muller, H., Awes, T. C., Martoiu, S., Kral, J., Silvermyr, D., … Zhou, D. (2014). Point-to-point readout for the ALICE EMCal detector. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 735, 157-162. doi:10.1016/j.nima.2013.09.023Martoiu, S., Muller, H., Tarazona, A., & Toledo, J. (2013). Development of the scalable readout system for micro-pattern gas detectors and other applications. Journal of Instrumentation, 8(03), C03015-C03015. doi:10.1088/1748-0221/8/03/c03015Toledo, J., Muller, H., Esteve, R., Monzó, J. M., Tarazona, A., & Martoiu, S. (2011). The Front-End Concentrator card for the RD51 Scalable Readout System. Journal of Instrumentation, 6(11), C11028-C11028. doi:10.1088/1748-0221/6/11/c11028Widmer, A. X., & Franaszek, P. A. (1983). A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code. IBM Journal of Research and Development, 27(5), 440-451. doi:10.1147/rd.275.0440Aliaga, R. J., Monzo, J. M., Spaggiari, M., Ferrando, N., Gadea, R., & Colom, R. J. (2011). PET System Synchronization and Timing Resolution Using High-Speed Data Links. IEEE Transactions on Nuclear Science, 58(4), 1596-1605. doi:10.1109/tns.2011.2140130Giordano, R., & Aloisio, A. (2011). Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs. IEEE Transactions on Nuclear Science, 58(1), 194-201. doi:10.1109/tns.2010.2101083Papakonstantinou, I., Soos, C., Papadopoulos, S., Detraz, S., Sigaud, C., Stejskal, P., … Darwazeh, I. (2011). A Fully Bidirectional Optical Network With Latency Monitoring Capability for the Distribution of Timing-Trigger and Control Signals in High-Energy Physics Experiments. IEEE Transactions on Nuclear Science, 58(4), 1628-1640. doi:10.1109/tns.2011.215436

Fronthaul evolution: From CPRI to Ethernet

It is proposed that using Ethernet in the fronthaul, between base station baseband unit (BBU) pools and remote radio heads (RRHs), can bring a number of advantages, from use of lower-cost equipment, shared use of infrastructure with fixed access networks, to obtaining statistical multiplexing and optimised performance through probe-based monitoring and software-defined networking. However, a number of challenges exist: ultra-high-bit-rate requirements from the transport of increased bandwidth radio streams for multiple antennas in future mobile networks, and low latency and jitter to meet delay requirements and the demands of joint processing. A new fronthaul functional division is proposed which can alleviate the most demanding bit-rate requirements by transport of baseband signals instead of sampled radio waveforms, and enable statistical multiplexing gains. Delay and synchronisation issues remain to be solved

MuPix7 - A fast monolithic HV-CMOS pixel chip for Mu3e

The MuPix7 chip is a monolithic HV-CMOS pixel chip, thinned down to 50 \mu m. It provides continuous self-triggered, non-shuttered readout at rates up to 30 Mhits/chip of 3x3 mm^2 active area and a pixel size of 103x80 \mu m^2. The hit efficiency depends on the chosen working point. Settings with a power consumption of 300 mW/cm^2 allow for a hit efficiency >99.5%. A time resolution of 14.2 ns (Gaussian sigma) is achieved. Latest results from 2016 test beam campaigns are shown.Comment: Proceedingsfor the PIXEL2016 conference, submitted to JINST A dangling reference has been removed from this version, no other change