An Assessment of Available Software Defined Radio Platforms Utilizing Iterative Algorithms

As the demands of communication systems have become more complex and varied, software defined radios (SDR) have become increasingly popular. With behavior that can be modified in software, SDR\u27s provide a highly flexible and configurable development environment. Despite its programmable behavior, the maximum performance of an SDR is still rooted in its hardware. This limitation and the desire for the use of SDRs in different applications have led to the rise of various pieces of hardware to serve as SDR platforms. These platforms vary in aspects such as their performance limitations, implementation details, and cost. In this way the choice of SDR platform is not solely based on the cost of the hardware and should be closely examined before making a final decision. This thesis examines the various SDR platform families available on the market today and compares the advantages and disadvantages present for each during development. As many different types of hardware can be considered an option to successfully implement an SDR, this thesis specifically focuses on general purpose processors, system on chip, and field-programmable gate array implementations. When examining these SDR families, the Freescale BSC9131 is chosen to represent the system on chip implementation, while the Nutaq PicoSDR 2x2 Embedded with Virtex6 SX315 is used for the remaining two options. In order to test each of these platforms, a Viterbi algorithm is implemented on each and the performance measured. This performance measurement considers both how quickly the platform is able to perform the decoding, as well as its bit error rate performance in order to ascertain the implementations\u27 accuracy. Other factors considered when comparing each platform are its flexibility and the amount of options available for development. After testing, the details of each implementation are discussed and guidelines for choosing a platform are suggested

Application of wavelets and artificial neural network for indoor optical wireless communication systems

Abstract This study investigates the use of error control code, discrete wavelet transform (DWT) and artificial neural network (ANN) to improve the link performance of an indoor optical wireless communication in a physical channel. The key constraints that barricade the realization of unlimited bandwidth in optical wavelengths are the eye-safety issue, the ambient light interference and the multipath induced intersymbol interference (ISI). Eye-safety limits the maximum average transmitted optical power. The rational solution is to use power efficient modulation techniques. Further reduction in transmitted power can be achieved using error control coding. A mathematical analysis of retransmission scheme is investigated for variable length modulation techniques and verified using computer simulations. Though the retransmission scheme is simple to implement, the shortfall in terms of reduced throughput will limit higher code gain. Due to practical limitation, the block code cannot be applied to the variable length modulation techniques and hence the convolutional code is the only possible option. The upper bound for slot error probability of the convolutional coded dual header pulse interval modulation (DH-PIM) and digital pulse interval modulation (DPIM) schemes are calculated and verified using simulations. The power penalty due to fluorescent light interference (FL I) is very high in indoor optical channel making the optical link practically infeasible. A denoising method based on a DWT to remove the FLI from the received signal is devised. The received signal is first decomposed into different DWT levels; the FLI is then removed from the signal before reconstructing the signal. A significant reduction in the power penalty is observed using DWT. Comparative study of DWT based denoising scheme with that of the high pass filter (HPF) show that DWT not only can match the best performance obtain using a HPF, but also offers a reduced complexity and design simplicity. The high power penalty due to multipath induced ISI makes a diffuse optical link practically infeasible at higher data rates. An ANN based linear and DF architectures are investigated to compensation the ISI. Unlike the unequalized cases, the equalized schemes don‘t show infinite power penalty and a significant performance improvement is observed for all modulation schemes. The comparative studies substantiate that ANN based equalizers match the performance of the traditional equalizers for all channel conditions with a reduced training data sequence. The study of the combined effect of the FLI and ISI shows that DWT-ANN based receiver perform equally well in the present of both interference. Adaptive decoding of error control code can offer flexibility of selecting the best possible encoder in a given environment. A suboptimal ?soft‘ sliding block convolutional decoder based on the ANN and a 1/2 rate convolutional code with a constraint length is investigated. Results show that the ANN decoder can match the performance of optimal Viterbi decoder for hard decision decoding but with slightly inferior performance compared to soft decision decoding. This provides a foundation for further investigation of the ANN decoder for convolutional code with higher constraint length values. Finally, the proposed DWT-ANN receiver is practically realized in digital signal processing (DSP) board. The output from the DSP board is compared with the computer simulations and found that the difference is marginal. However, the difference in results doesn‘t affect the overall error probability and identical error probability is obtained for DSP output and computer simulations

New VLSI design of a MAP/BCJR decoder.

Any communication channel suffers from different kinds of noises. By employing forward error correction (FEC) techniques, the reliability of the communication channel can be increased. One of the emerging FEC methods is turbo coding (iterative coding), which employs soft input soft output (SISO) decoding algorithms like maximum a posteriori (MAP) algorithm in its constituent decoders. In this thesis we introduce a design with lower complexity and less than 0.1dB performance loss compare to the best performance observed in Max-Log-MAP algorithm. A parallel and pipeline design of a MAP decoder suitable for ASIC (Application Specific Integrated Circuits) is used to increase the throughput of the chip. The branch metric calculation unit is studied in detail and a new design with lower complexity is proposed. The design is also flexible to communication block sizes, which makes it ideal for variable frame length communication systems. A new even-spaced quantization technique for the proposed MAP decoder is utilized. Normalization techniques are studied and a suitable technique for the Max-Log-MAP decoder is explained. The decoder chip is synthesized and implemented in a 0.18 mum six-layer metal CMOS technology. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .S23. Source: Masters Abstracts International, Volume: 43-05, page: 1783. Adviser: Majid Ahmadi. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

ON REDUCING THE DECODING COMPLEXITY OF SHINGLED MAGNETIC RECORDING SYSTEM

Shingled Magnetic Recording (SMR) has been recognised as one of the alternative technologies to achieve an areal density beyond the limit of the perpendicular recording technique, 1 Tb/in2, which has an advantage of extending the use of the conventional method media and read/write head. This work presents SMR system subject to both Inter Symbol Interference (ISI) and Inter Track Interference (ITI) and investigates different equalisation/detection techniques in order to reduce the complexity of this system. To investigate the ITI in shingled systems, one-track one-head system model has been extended into two-track one-head system model to have two interfering tracks. Consequently, six novel decoding techniques have been applied to the new system in order to find the Maximum Likelihood (ML) sequence. The decoding complexity of the six techniques has been investigated and then measured. The results show that the complexity is reduced by more than three times with 0.5 dB loss in performance. To measure this complexity practically, perpendicular recording system has been implemented in hardware. Hardware architectures are designed for that system with successful Quartus II fitter which are: Perpendicular Magnetic Recording (PMR) channel, digital filter equaliser with and without Additive White Gaussian Noise (AWGN) and ideal channel architectures. Two different hardware designs are implemented for Viterbi Algorithm (VA), however, Quartus II fitter for both of them was unsuccessful. It is found that, Simulink/Digital Signal Processing (DSP) Builder based designs are not efficient for complex algorithms and the eligible solution for such designs is writing Hardware Description Language (HDL) codes for those algorithms.The Iraqi Governmen

An 8-DPSK TCM modem for MSAT-X

This paper describes the real-time digital implementation of an 8-differentiated phase-shift keying (DPSK) trellis-coded modulation (TCM) modem for operation on an L-band, 5 kHz wide, land mobile satellite (LMS) channel. The modem architecture as well as some of the signal processing techniques employed in the modem to combat the LMS channel impairments are described, and the modem performance over the fading channel is presented