Physical Layer Techniques for High Frequency Wireline Broadband Systems

This thesis collects contributions to wireline and wireless communication systems with an emphasis on multiuser and multicarrier physical layer technology. To deliver increased capacity, modern wireline access systems such as G.fast extend the signal bandwidth up from tens to hundreds of MHz. This ambitious development revealed a number of unforeseen hurdles such as the impact of impedance changes in various forms. Impedance changes have a strong effect on the performance of multi-user crosstalk mitigation techniques such as vectoring. The first part of the thesis presents papers covering the identification of one of these problems, a model describing why it occurs and a method to mitigate its effects, improving line stability for G.fast systems.A second part of the thesis deals with the effects of temperature changes on wireline channels. When a vectored (MIMO) wireline system is initialized, channel estimates need to be obtained. This thesis presents contributions on the feasibility of re-using channel coefficients to speed up the vectoring startup procedures, even after the correct coefficients have changed, e.g., due to temperature changes. We also present extensive measurement results showing the effects of temperature changes on copper channels using a temperature chamber and British cables. The last part of the thesis presents three papers on the convergence of physical layer technologies, more specifically the deployment of OFDM-based radio systems using twisted pairs in different ways. In one proposed scenario, the idea of using the access copper lines to deploy small cells inside users' homes is explored. The feasibility of the concept, the design of radio-heads and a practical scheme for crosstalk mitigation are presented in three contributions

Performance evaluation of currently available VLSI implementations satisfying U-interface requirements for an ISDN in South Africa.

A project report submitted to the Faculty of Engineering, University of the Witwatersrand, Johannesburg, in partial fulfilment of the requirements for the degree of Master of Science in Engineering.This project report examines the performance of three VLSI U-interface implementations satisfying the requirements of Basic Access on an ISDN. The systems evaluated are the Intel 89120,Siemens PEB2090 and STC DSP144, operating on 2BIQ, MMS4J and SU32 line codes respectively. Before evaluating the three abovementioned systems, a review of the underlying principles of U-interface technology is presented. Included in the review are aspects of transmission line theory, line coding, echo-cancellation, decision feedback equalisation, and pulse density modulation. The functional specifications of the three systems are then presented followed by a practical evaluation of each system. As an aid to testing the transmission systems, an evaluation board has been designed and built. The latter provides the necessary functionality to correctly activate each system, as well as the appropriate interfacing requirements for the error-rate tester. The U-interface transmission systems are evaluated on a number of test-loops, comprising sections of cable varying in length and gauge. Additionally, impairments are injected into data-carrying cables, in order to test the performance of each system in the presence of noise. The results of each test are recorded and analysed. Finally, a recommendation is made in favour of the 2BIQ U-interface. It is shown to offer superior transmission performance, at the expense of a slightly higher transmit-power level.Andrew Chakane 201

Simple Statistical Analysis of the Impact of Some Nonidealities in Downstream VDSL with Linear Precoding

Abstract This paper considers a VDSL downstream system where crosstalk is compensated by linear precoding. Starting from a recently introduced mathematical model for FEXT channels, simple analytical methods are derived for evaluating the average bit rates achievable, taking into account three of the most important nonidealities. First, absolute and relative estimation errors in the crosstalk coefficients are discussed, and explicit formulas are obtained to express their impact. A simple approach is presented for computing the maximum line length where linear precoding overcomes the noncoordinate system. Then, the effect of out-of-domain crosstalk is analyzed. Finally, quantization errors in precoding coefficients are considered. We show that by the assumption of a midtread quantization law with different thresholds, a relatively small number of quantization bits is sufficient, thus reducing the implementation complexity. The presented formulas allow to quantify the impact of practical impairments and give a useful tool to design engineers and service providers to have a first estimation of the performance achievable in a specified scenario

Analog Compressive Sensing for Multi-Channel Neural Recording: Modeling and Circuit Level Implementation

RÉSUMÉ Dans cette thèse, nous présentons la conception d’un implant d’enregistrement neuronal multicanaux avec un échantillonnage compressé mis en oeuvre avec un procédé de fabrication CMOS à 65 nm. La réduction de la technologie a˙ecte à la baisse les paramètres des amplificateurs neuronaux couplés en AC, comme la fréquence de coupure basse, en raison de l’e˙et de canal court des transistors MOS. Nous analysons la fréquence de coupure basse et nous constatons que l’origine de ce problème, dans les technologies avancées, est la diminution de l’impédance d’entrée de l’amplificateur opérationnel de transconductance (OTA) en raison de la fuite d’oxyde de grille à l’entrée des OTA. Nous proposons deux solutions pour réduire la fréquence de coupure basse sans augmenter la valeur des condensateurs de rétroaction de l’étage d’entrée. La première solution est appelée rétroaction positive croisée et la deuxième solution utilise des PMOS à oxyde épais dans la paire de l’entrée di˙érentielle de l’OTA. Il est à noter que pour compresser le signal neuronal, nous utilisons le CS dans le domaine analogique. Pour la réalisation, un intégrateur à capacité commutée est requis. Les paramètres non idéaux de l’OTA utilisé dans cet intégrateur, tels que le gain fini, la bande passante, la vitesse de balayage et le changement rapide de la sortie. Toutes ces imperfections induisent des erreurs et réduisent le rapport signal sur bruit (SNR) total. Nous avons simulé ces imperfections sur Matlab et Simulink pour définir les spécifications de l’OTA requis. Aussi, pour concevoir les circuits analogiques correspondant aux interfaces neuronales requises, tels qu’un amplificateur neuronal, une référence de tension compacte et à faible consommation d’énergie est requise. Nous avons proposé une référence de tension de faible consommation d’énergie sans utiliser le transistor bipolaire parasite de la technologie CMOS pour diminuer la surface de silicium requise. Finalement, nous avons complété l’encodeur de CS et un convertisseur analogique-numérique à approximation successive (SAR ADC) requis pour la chaine d’enregistrement des signaux neuronaux dans ce projet.----------ABSTRACT In this thesis we present the design of a multi-channel neural recording implant with analog compressive sensing (CS) in 65 nm process. Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cuto˙ frequency due to the short-channel e˙ects of MOS transistors. We analyze the low-cuto˙ frequency and find that the main reason of this problem in advanced technologies is decreasing the input resistance of the operational transconductance amplifier (OTA) due to the gate oxide static current leakage in the input of the OTA. In advanced technologies, the gate oxide is thin and some electrons can penetrate to the channel and cause DC current leakage. We proposed two solutions to reduce the low-cuto˙ frequency without increasing the value of the feedback capacitors of the front-end neural amplifier. The first solution is called cross-coupled positive feedback, and the second solution is utilizing thick-oxide PMOS transistors in the input di˙erential pair of the OTA. Compress the neural signal, we utilized the CS method in analog domain. For its implementation, a switched-capacitor integrator is required. Non-ideal specifications of OTA of CS integrator such as finite gain, bandwidth, slew rate and output swing induce error and reduce the total signal to noise ratio (SNR). We simulated these non-idealities in Matlab and Simulink and extracted the specification of the required OTA. Also, to design analog circuits such as neural amplifier a low power and compact voltage reference is required. We implemented a low-power band-gap reference without utilizing parasitic bipolar transis-tor to decrease the silicon area. At the end, we completed the CS encoder and successive approximation architecture analog-to-digital converter (SAR ADC)

Engineering evaluations and studies. Volume 3: Exhibit C

High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed

Estimation and detection of transmission line characteristics in the copper access network

The copper access-network operators face the challenge of developing and maintaining cost-effective digital subscriber line (DSL) services that are competitive to other broadband access technologies. The way forward is dictated by the demand of ever increasing data rates on the twisted-pair copper lines. To meet this demand, a relocation of the DSL transceivers in cabinets closer to the customers are often necessary combined with a joint expansion of the accompanying optical-fiber backhaul network. The equipment of the next generation copper network are therefore becoming more scattered and geographically distributed, which increases the requirements of automated line qualification with fault detection and localization. This scenario is addressed in the first five papers of this dissertation where the focus is on estimation and detection of transmission line characteristics in the copper access network. The developed methods apply model-based optimization with an emphasis on using low-order modeling and a priori information of the given problem. More specifically, in Paper I a low-order and causal cable model is derived based on the Hilbert transform. This model is successfully applied in three contributions of this dissertation. In Paper II, a class of low-complexity unbiased estimators for the frequency-dependent characteristic impedance is presented that uses one-port measurements only. The so obtained characteristic impedance paves the way for enhanced time domain reflectometry (a.k.a. TDR) on twisted-pair lines. In Paper III, the problem of estimating a nonhomogeneous and dispersive transmission line is investigated and a space-frequency optimization approach is developed for the DSL application. The accompanying analysis shows which parameters are of interest to estimate and further suggests the introduction of the concept capacitive length that overcomes the necessity of a priori knowledge of the physical line length. In Paper IV, two methods are developed for detection and localization of load coils present in so-called loaded lines. In Paper V, line topology identification is addressed with varying degree of a priori information. In doing so, a model-based optimization approach is employed that utilizes multi-objective evolutionary computation based on one/two-port measurements. A complement to transceiver relocation that potentially enhances the total data throughput in the copper access network is dynamic spectrum management (DSM). This promising multi-user transmission technique aims at maximizing the transmission rates, and/or minimizing the power consumption, by mitigating or cancelling the dominating crosstalk interference between twisted-pair lines in the same cable binder. Hence the spectral utilization is improved by optimizing the transmit signals in order to minimize the crosstalk interference. However, such techniques rely on accurate information of the (usually) unknown crosstalk channels. This issue is the main focus of Paper VI and VII of this dissertation in which Paper VI deals with estimation of the crosstalk channels between twisted-pair lines. More specifically, an unbiased estimator for the square-magnitude of the crosstalk channels is derived from which a practical procedure is developed that can be implemented with standardized DSL modems already installed in the copper access network. In Paper VII the impact such a non-ideal estimator has on the performance of DSM is analyzed and simulated. Finally, in Paper VIII a novel echo cancellation algorithm for DMT-based DSL modems is presented

Adaptive multilevel quadrature amplitude radio implementation in programmable logic

Emerging broadband wireless packet data networks are increasingly employing spectrally efficient modulation methods like Quadrature Amplitude Modulation (QAM) to increase the channel efficiency and maximize data throughput. Unfortunately, the performance of high level QAM modulations in the wireless channel is sensitive to channel imperfections and throughput is degraded significantly at low signal-to-noise ratios due to bit errors and packet retransmission. To obtain a more “robust” physical layer, broadband systems are employing multilevel QAM (M-QAM) to mitigate this reduction in throughput by adapting the QAM modulation level to maintain acceptable packet error rate (PER) performance in changing channel conditions. This thesis presents an adaptive M-QAM modem hardware architecture, suitable for use as a modem core for programmable software defined radios (SDRs) and broadband wireless applications. The modem operates in “burst” mode, and can reliably synchronize to different QAM constellations “burst-by-burst”. Two main improvements exploit commonality in the M-QAM constellations to minimize the redundant hardware required. First, the burst synchronization functions (carrier, clock, amplitude, and modulation level) operate reliably without prior knowledge of the QAM modulation level used in the burst. Second, a unique bit stuffing and shifting technique is employed which supports variable bit rate operation, while reducing the core signal processing functions to common hardware for all constellations. These features make this architecture especially attractive for implementation with Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs); both of which are becoming popular for highly integrated, cost-effective wireless transceivers