VLSI decoding architectures: flexibility, robustness and performance

Stemming from previous studies on flexible LDPC decoders, this thesis work has been mainly focused on the development of flexible turbo and LDPC decoder designs, and on the narrowing of the power, area and speed gap they might present with respect to dedicated solutions. Additional studies have been carried out within the field of increased code performance and of decoder resiliency to hardware errors. The first chapter regroups several main contributions in the design and implementation of flexible channel decoders. The first part concerns the design of a Network-on-Chip (NoC) serving as an interconnection network for a partially parallel LDPC decoder. A best-fit NoC architecture is designed and a complete multi-standard turbo/LDPC decoder is designed and implemented. Every time the code is changed, the decoder must be reconfigured. A number of variables influence the duration of the reconfiguration process, starting from the involved codes down to decoder design choices. These are taken in account in the flexible decoder designed, and novel traffic reduction and optimization methods are then implemented. In the second chapter a study on the early stopping of iterations for LDPC decoders is presented. The energy expenditure of any LDPC decoder is directly linked to the iterative nature of the decoding algorithm. We propose an innovative multi-standard early stopping criterion for LDPC decoders that observes the evolution of simple metrics and relies on on-the-fly threshold computation. Its effectiveness is evaluated against existing techniques both in terms of saved iterations and, after implementation, in terms of actual energy saving. The third chapter portrays a study on the resilience of LDPC decoders under the effect of memory errors. Given that the purpose of channel decoders is to correct errors, LDPC decoders are intrinsically characterized by a certain degree of resistance to hardware faults. This characteristic, together with the soft nature of the stored values, results in LDPC decoders being affected differently according to the meaning of the wrong bits: ad-hoc error protection techniques, like the Unequal Error Protection devised in this chapter, can consequently be applied to different bits according to their significance. In the fourth chapter the serial concatenation of LDPC and turbo codes is presented. The concatenated FEC targets very high error correction capabilities, joining the performance of turbo codes at low SNR with that of LDPC codes at high SNR, and outperforming both current deep-space FEC schemes and concatenation-based FECs. A unified decoder for the concatenated scheme is subsequently propose

Cooperative diversity techniques for future wireless communications systems.

Thesis (Ph.D.)-University of KwaZulu-Natal, Durban, 2013.Multiple-input multiple-output (MIMO) systems have been extensively studied in the past decade. The attractiveness of MIMO systems is due to the fact that they drastically reduce the deleterious e ects of multipath fading leading to high system capacity and low error rates. In situations where wireless devices are restrained by their size and hardware complexity, such as mobile phones, transmit diversity is not achievable. A new paradigm called cooperative communication is a viable solution. In a cooperative scenario, a single-antenna device is assisted by another single-antenna device to relay its message to the destination or base station. This creates a virtual multiple-input multiple-output (MIMO) system. There exist two cooperative strategies: amplify-and-forward (AF) and decode-and-forward (DF). In the former, the relay ampli es the noisy signal received from the source before forwarding it to the destination. No form of demodulation is required. In the latter, the relay rst decodes the source signal before transmitting an estimate to the destination. In this work, focus is on the DF method. A drawback of an uncoded DF cooperative strategy is error propagation at the relay. To avoid error propagation in DF, various relay selection schemes can be used. Coded cooperation can also be used to avoid error propagation at the relay. Various error correcting codes such as convolutional codes or turbo codes can be used in a cooperative scenario. The rst part of this work studies a variation of the turbo codes in cooperative diversity, that further reduces error propagation at the relay, hence lowering the end-to-end error rate. The union bounds on the bit-error rate (BER) of the proposed scheme are derived using the pairwise error probability via the transfer bounds and limit-before-average techniques. In addition, the outage analysis of the proposed scheme is presented. Simulation results of the bit error and outage probabilities are presented to corroborate the analytical work. In the case of outage probability, the computer simulation results are in good agreement with the the analytical framework presented in this chapter. Recently, most studies have focused on cross-layer design of cooperative diversity at the physical layer and truncated automatic-repeat request (ARQ) at the data-link layer using the system throughput as the performance metric. Various throughput optimization strategies have been investigated. In this work, a cross-relay selection approach that maximizes the system throughput is presented. The cooperative network is comprised of a set of relays and the reliable relay(s) that maximize the throughput at the data-link layer are selected to assist the source. It can be shown through simulation that this novel scheme outperforms from a throughput point of view, a system throughput where the all the reliable relays always participate in forwarding the source packet. A power optimization of the best relay uncoded DF cooperative diversity is investigated. This optimization aims at maximizing the system throughput. Because of the non-concavity and non-convexity of the throughput expression, it is intractable to derive a closed-form expression of the optimal power through the system throughput. However, this can be done via the symbol-error rate (SER) optimization, since it is shown that minimizing the SER of the cooperative system is equivalent to maximizing the system throughput. The SER of the retransmission scheme at high signal-to-noise ratio (SNR) was obtained and it was noted that the derived SER is in perfect agreement with the simulated SER at high SNR. Moreover, the optimal power allocation obtained under a general optimization problem, yields a throughput performance that is superior to non-optimized power values from moderate to high SNRs. The last part of the work considers the throughput maximization of the multi-relay adaptive DF over independent and non-identically distributed (i.n.i.d.) Rayleigh fading channels, that integrates ARQ at the link layer. The aim of this chapter is to maximize the system throughput via power optimization and it is shown that this can be done by minimizing the SER of the retransmission. Firstly, the closed-form expressions for the exact SER of the multi-relay adaptive DF are derived as well as their corresponding asymptotic bounds. Results showed that the optimal power distribution yields maximum throughput. Furthermore, the power allocated at a relay is greatly dependent of its location relative to the source and destination

Communications protocols for wireless sensor networks in perturbed environment

This thesis is mainly in the Smart Grid (SG) domain. SGs improve the safety of electrical networks and allow a more adapted use of electricity storage, available in a limited way. SGs also increase overall energy efficiency by reducing peak consumption. The use of this technology is the most appropriate solution because it allows more efficient energy management. In this context, manufacturers such as Hydro-Quebec deploy sensor networks in the nerve centers to control major equipment. To reduce deployment costs and cabling complexity, the option of a wireless sensor network seems the most obvious solution. However, deploying a sensor network requires in-depth knowledge of the environment. High voltages substations are strategic points in the power grid and generate impulse noise that can degrade the performance of wireless communications. The works in this thesis are focused on the development of high performance communication protocols for the profoundly disturbed environments. For this purpose, we have proposed an approach based on the concatenation of rank metric and convolutional coding with orthogonal frequency division multiplexing. This technique is very efficient in reducing the bursty nature of impulsive noise while having a quite low level of complexity. Another solution based on a multi-antenna system is also designed. We have proposed a cooperative closed-loop coded MIMO system based on rank metric code and max−dmin precoder. The second technique is also an optimal solution for both improving the reliability of the system and energy saving in wireless sensor networks

Satellite Communications

This study is motivated by the need to give the reader a broad view of the developments, key concepts, and technologies related to information society evolution, with a focus on the wireless communications and geoinformation technologies and their role in the environment. Giving perspective, it aims at assisting people active in the industry, the public sector, and Earth science fields as well, by providing a base for their continued work and thinking

Third International Symposium on Space Mission Operations and Ground Data Systems, part 2

Under the theme of 'Opportunities in Ground Data Systems for High Efficiency Operations of Space Missions,' the SpaceOps '94 symposium included presentations of more than 150 technical papers spanning five topic areas: Mission Management, Operations, Data Management, System Development, and Systems Engineering. The symposium papers focus on improvements in the efficiency, effectiveness, and quality of data acquisition, ground systems, and mission operations. New technology, methods, and human systems are discussed. Accomplishments are also reported in the application of information systems to improve data retrieval, reporting, and archiving; the management of human factors; the use of telescience and teleoperations; and the design and implementation of logistics support for mission operations. This volume covers expert systems, systems development tools and approaches, and systems engineering issues

Fault-tolerant satellite computing with modern semiconductors

Miniaturized satellites enable a variety space missions which were in the past infeasible, impractical or uneconomical with traditionally-designed heavier spacecraft. Especially CubeSats can be launched and manufactured rapidly at low cost from commercial components, even in academic environments. However, due to their low reliability and brief lifetime, they are usually not considered suitable for life- and safety-critical services, complex multi-phased solar-system-exploration missions, and missions with a longer duration. Commercial electronics are key to satellite miniaturization, but also responsible for their low reliability: Until 2019, there existed no reliable or fault-tolerant computer architectures suitable for very small satellites. To overcome this deficit, a novel on-board-computer architecture is described in this thesis.Robustness is assured without resorting to radiation hardening, but through software measures implemented within a robust-by-design multiprocessor-system-on-chip. This fault-tolerant architecture is component-wise simple and can dynamically adapt to changing performance requirements throughout a mission. It can support graceful aging by exploiting FPGA-reconfiguration and mixed-criticality.  Experimentally, we achieve 1.94W power consumption at 300Mhz with a Xilinx Kintex Ultrascale+ proof-of-concept, which is well within the powerbudget range of current 2U CubeSats. To our knowledge, this is the first COTS-based, reproducible on-board-computer architecture that can offer strong fault coverage even for small CubeSats.European Space AgencyComputer Systems, Imagery and Medi

Hardware realization of discrete wavelet transform cauchy Reed Solomon minimal instruction set computer architecture for wireless visual sensor networks

Large amount of image data transmitting across the Wireless Visual Sensor Networks (WVSNs) increases the data transmission rate thus increases the power transmission. This would inevitably decreases the operating lifespan of the sensor nodes and affecting the overall operation of WVSNs. Limiting power consumption to prolong battery lifespan is one of the most important goals in WVSNs. To achieve this goal, this thesis presents a novel low complexity Discrete Wavelet Transform (DWT) Cauchy Reed Solomon (CRS) Minimal Instruction Set Computer (MISC) architecture that performs data compression and data encoding (encryption) in a single architecture. There are four different programme instructions were developed to programme the MISC processor, which are Subtract and Branch if Negative (SBN), Galois Field Multiplier (GF MULT), XOR and 11TO8 instructions. With the use of these programme instructions, the developed DWT CRS MISC were programmed to perform DWT image compression to reduce the image size and then encode the DWT coefficients with CRS code to ensure data security and reliability. Both compression and CRS encoding were performed by a single architecture rather than in two separate modules which require a lot of hardware resources (logic slices). By reducing the number of logic slices, the power consumption can be subsequently reduced. Results show that the proposed new DWT CRS MISC architecture implementation requires 142 Slices (Xilinx Virtex-II), 129 slices (Xilinx Spartan-3E), 144 Slices (Xilinx Spartan-3L) and 66 Slices (Xilinx Spartan-6). The developed DWT CRS MISC architecture has lower hardware complexity as compared to other existing systems, such as Crypto-Processor in Xilinx Spartan-6 (4828 Slices), Low-Density Parity-Check in Xilinx Virtex-II (870 slices) and ECBC in Xilinx Spartan-3E (1691 Slices). With the use of RC10 development board, the developed DWT CRS MISC architecture can be implemented onto the Xilinx Spartan-3L FPGA to simulate an actual visual sensor node. This is to verify the feasibility of developing a joint compression, encryption and error correction processing framework in WVSNs

Hardware realization of discrete wavelet transform cauchy Reed Solomon minimal instruction set computer architecture for wireless visual sensor networks

Large amount of image data transmitting across the Wireless Visual Sensor Networks (WVSNs) increases the data transmission rate thus increases the power transmission. This would inevitably decreases the operating lifespan of the sensor nodes and affecting the overall operation of WVSNs. Limiting power consumption to prolong battery lifespan is one of the most important goals in WVSNs. To achieve this goal, this thesis presents a novel low complexity Discrete Wavelet Transform (DWT) Cauchy Reed Solomon (CRS) Minimal Instruction Set Computer (MISC) architecture that performs data compression and data encoding (encryption) in a single architecture. There are four different programme instructions were developed to programme the MISC processor, which are Subtract and Branch if Negative (SBN), Galois Field Multiplier (GF MULT), XOR and 11TO8 instructions. With the use of these programme instructions, the developed DWT CRS MISC were programmed to perform DWT image compression to reduce the image size and then encode the DWT coefficients with CRS code to ensure data security and reliability. Both compression and CRS encoding were performed by a single architecture rather than in two separate modules which require a lot of hardware resources (logic slices). By reducing the number of logic slices, the power consumption can be subsequently reduced. Results show that the proposed new DWT CRS MISC architecture implementation requires 142 Slices (Xilinx Virtex-II), 129 slices (Xilinx Spartan-3E), 144 Slices (Xilinx Spartan-3L) and 66 Slices (Xilinx Spartan-6). The developed DWT CRS MISC architecture has lower hardware complexity as compared to other existing systems, such as Crypto-Processor in Xilinx Spartan-6 (4828 Slices), Low-Density Parity-Check in Xilinx Virtex-II (870 slices) and ECBC in Xilinx Spartan-3E (1691 Slices). With the use of RC10 development board, the developed DWT CRS MISC architecture can be implemented onto the Xilinx Spartan-3L FPGA to simulate an actual visual sensor node. This is to verify the feasibility of developing a joint compression, encryption and error correction processing framework in WVSNs