High speed protocols for dual bus and dual ring network architectures

In this dissertation, two channel access mechanisms providing fair and bandwidth efficient transmission on dual bus and dual ring networks with high bandwidth-latency product are proposed. In addition, two effective priority mechanisms are introduced to meet the throughput and delay requirements of the diverse arrays of applications that future high speed networks must support. For dual bus architectures, the Buffer Insertion Bandwidth Balancing (BI_BWB) mechanism and the Preemptive priority Bandwidth Balancing (P_BI_BWB) mechanism are proposed. BI_BWB can significantly improve the delay performance of remote stations. It achieves that by providing each station with a shift register into which the station can temporarily store the upstream stations\u27 transmitted packets and replace these packets with its own transmissions. P_BI_BWB, an enhancement of BI_BWB, is designed to introduce effective preemptive priorities. This mechanism eliminates the effect of low priority on high priority by buffering the low priority traffic into a shift register until the transmission of the high priority traffic is complete. For dual ring architectures, the Fair Bandwidth Allocation Mechanism (FBAM) and the Effective Priority Bandwidth Balancing (EP_BWB) mechanism are introduced. FBAM allows stations to reserve channel bandwidth on a continuous basis rather than wait until bandwidth starvation is observed. Consequently, FBAM does not have to deal with the difficult issue of identifying starvation, a serious drawback of other access mechanisms such as the Local and Global Fairness Algorithms (LFA and GFA, respectively). In addition, its operation requires a significantly smaller number of control bits in the access control field of the slot and its performance is less sensitive to system parameters. Moreover, FBAM demonstrates Max-Min flow control properties with respect to the allocation of bandwidth among competing traffic streams, which is a significant advantage of FBAM over all the previously proposed channel access mechanisms. EP_BWB, an enhancement of FBAM to support preemptive priorities, minimizes the effect of low priority on high priority and supports delay-sensitive traffic by enabling higher priority classes to preempt the transmissions of lower priority classes. Finally, the great potential of EP_BWB to support the interconnection of base stations on a distributed control wireless PCN carrying voice and data traffic is demonstrated

Performance Improvements for FDDI and CSMA/CD Protocols

The High-Performance Computing Initiative from the White House Office of Science and Technology Policy has defined 20 major challenges in science and engineering which are dependent on the solutions to a number of high-performance computing problems. One of the major areas of focus of this initiative is the development of gigabit rate networks to be used in environments such as the space station or a National Research and Educational Network (NREN). The strategy here is to use existing network designs as building blocks for achieving higher rates, with the ultimate goal being a gigabit rate network. Two strategies which contribute to achieving this goal are examined in detail.1 FDDI2 is a token ring network based on fiber optics capable of a 100 Mbps rate. Both media access (MAC) and physical layer modifications are considered. A method is presented which allows one to determine maximum utilization based on the token-holding timer settings. Simulation results show that employing the second counter-rotating ring in combination with destination removal has a multiplicative effect greater than the effect which either of the factors have individually on performance. Two 100 Mbps rings can handle loads in the range of 400 to 500 Mbps for traffic with a uniform distribution and fixed packet size. Performance is dependent on the number of nodes, improving as the number increases. A wide range of environments are examined to illustrate robustness, and a method of implementation is discussed

Some topics in web performance analysis

This thesis consists of four papers on web performance analysis. In the first paper we investigate the performance of overload control through queue length for two different web server architectures. The simulation result suggests that the benefit of request prioritization is noticeable only when the capacities of the sub-systems match each other. In the second paper we present an M/G/1/K*PS queueing model of a web server. We obtain closed form expressions for web server performance metrics such as average response time, throughput and blocking probability. The model is validated through real measurements. The third paper studies a queueing system with a load balancer and a pool of identical FCFS queues in parallel. By taking the number of servers to infinite, we show that the average waiting time for the system is not always minimized by routing each customer to the expected shortest queue when the information used for decision is stale. In the last paper we consider the problem of admission control to an M/M/1 queue under periodic observations with average cost criterion. The problem is formulated as a discrete time Markov decision process whose states are fully observable. A proof of the existence of the average optimal policy by the vanishing discounted approach is provided. We also show that the optimal policy is nonincreasing with respect to the observed number of customers in the system

Design and implementation of high speed multimedia network.

by Yeung Chung Toa.Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.Includes bibliographical references (leaves 63-[65]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Bandwidth required by multimedia applications --- p.1Chapter 1.2 --- Real-time requirement --- p.2Chapter 1.3 --- Multicasting --- p.2Chapter 1.4 --- Other networks --- p.3Chapter 1.5 --- Overview of CUM LAUDE NET --- p.5Chapter 1.5.1 --- Protocols --- p.7Chapter 1.5.2 --- Network Services --- p.8Chapter 1.6 --- Scope of the Thesis --- p.9Chapter 2 --- Network Architecture --- p.11Chapter 2.1 --- CUM LAUDE NET Architectural Overview --- p.11Chapter 2.2 --- Level One Network Architecture --- p.12Chapter 2.3 --- Level-One Router --- p.14Chapter 2.3.1 --- packet forwarding --- p.14Chapter 2.3.2 --- packet insertion --- p.15Chapter 2.3.3 --- packet removal --- p.15Chapter 2.3.4 --- fault protection --- p.15Chapter 2.4 --- Hub --- p.16Chapter 2.5 --- Host & Network Interface Card --- p.17Chapter 3 --- Protocol --- p.19Chapter 3.1 --- Design Overview --- p.19Chapter 3.2 --- Layering --- p.20Chapter 3.3 --- "Segment, Datagram, and Packet Format" --- p.21Chapter 3.3.1 --- IP/VCI field --- p.23Chapter 3.4 --- Data Link --- p.23Chapter 3.4.1 --- byte format and data link synchronization --- p.23Chapter 3.4.2 --- access control byte --- p.24Chapter 3.4.3 --- packet/frame boundary --- p.26Chapter 3.5 --- Fast Packet Routing Protocol --- p.26Chapter 3.5.1 --- Level-2/Level-l Bridge/Router --- p.27Chapter 3.5.2 --- Level-1 Hub --- p.29Chapter 3.5.3 --- Local Host NIC --- p.29Chapter 3.6 --- Media Access Control Protocol I : ACTA --- p.30Chapter 3.7 --- Media Access Control Protocol II: Hub Polling --- p.34Chapter 3.8 --- Protocol Implementation on CUM LAUDE NET --- p.36Chapter 4 --- Hardware Implementation & Performance of Routers and NIC --- p.40Chapter 4.1 --- Functionality of Router --- p.40Chapter 4.2 --- Important Components Used in the Router Design --- p.43Chapter 4.2.1 --- TAXI Transmitter and Receiver --- p.43Chapter 4.2.2 --- First-In-First-Out Memory (FIFO) --- p.44Chapter 4.3 --- Design of Router --- p.45Chapter 4.3.1 --- Version 1 --- p.45Chapter 4.3.2 --- Version 2 --- p.47Chapter 4.3.3 --- Version 3 --- p.50Chapter 4.4 --- Lessons Learned from the High Speed Router Design --- p.57Chapter 5 --- Conclusion --- p.61Bibliography --- p.6

Performance modeling and control of web servers

This thesis deals with the task of modeling a web server and designing a mechanism that can prevent the web server from being overloaded. Four papers are presented. The first paper gives an M/G/1/K processor sharing model of a single web server. The model is validated against measurements ands imulations on the commonly usedw eb server Apache. A description is given on how to calculate the necessary parameters in the model. The second paper introduces an admission control mechanism for the Apache web server basedon a combination of queuing theory andcon trol theory. The admission control mechanism is tested in the laboratory, implemented as a stand-alone application in front of the web server. The third paper continues the work from the secondp aper by discussing stability. This time, the admission control mechanism is implemented as a module within the Apache source code. Experiments show the stability and settling time of the controller. Finally, the fourth paper investigates the concept of service level agreements for a web site. The agreements allow a maximum response time anda minimal throughput to be set. The requests are sorted into classes, where each class is assigneda weight (representing the income for the web site owner). Then an optimization algorithm is appliedso that the total profit for the web site during overload is maximized

Distributed multimedia systems

A distributed multimedia system (DMS) is an integrated communication, computing, and information system that enables the processing, management, delivery, and presentation of synchronized multimedia information with quality-of-service guarantees. Multimedia information may include discrete media data, such as text, data, and images, and continuous media data, such as video and audio. Such a system enhances human communications by exploiting both visual and aural senses and provides the ultimate flexibility in work and entertainment, allowing one to collaborate with remote participants, view movies on demand, access on-line digital libraries from the desktop, and so forth. In this paper, we present a technical survey of a DMS. We give an overview of distributed multimedia systems, examine the fundamental concept of digital media, identify the applications, and survey the important enabling technologies.published_or_final_versio

Regular Topologies for Gigabit Wide-Area Networks

In general terms, this project aimed at the analysis and design of techniques for very high-speed networking. The formal objectives of the project were to: (1) Identify switch and network technologies for wide-area networks that interconnect a large number of users and can provide individual data paths at gigabit/s rates; (2) Quantitatively evaluate and compare existing and proposed architectures and protocols, identify their strength and growth potentials, and ascertain the compatibility of competing technologies; and (3) Propose new approaches to existing architectures and protocols, and identify opportunities for research to overcome deficiencies and enhance performance. The project was organized into two parts: 1. The design, analysis, and specification of techniques and protocols for very-high-speed network environments. In this part, SRI has focused on several key high-speed networking areas, including Forward Error Control (FEC) for high-speed networks in which data distortion is the result of packet loss, and the distribution of broadband, real-time traffic in multiple user sessions. 2. Congestion Avoidance Testbed Experiment (CATE). This part of the project was done within the framework of the DARTnet experimental T1 national network. The aim of the work was to advance the state of the art in benchmarking DARTnet's performance and traffic control by developing support tools for network experimentation, by designing benchmarks that allow various algorithms to be meaningfully compared, and by investigating new queueing techniques that better satisfy the needs of best-effort and reserved-resource traffic. This document is the final technical report describing the results obtained by SRI under this project. The report consists of three volumes: Volume 1 contains a technical description of the network techniques developed by SRI in the areas of FEC and multicast of real-time traffic. Volume 2 describes the work performed under CATE. Volume 3 contains the source code of all software developed under CATE

Satellite Networks: Architectures, Applications, and Technologies

Since global satellite networks are moving to the forefront in enhancing the national and global information infrastructures due to communication satellites' unique networking characteristics, a workshop was organized to assess the progress made to date and chart the future. This workshop provided the forum to assess the current state-of-the-art, identify key issues, and highlight the emerging trends in the next-generation architectures, data protocol development, communication interoperability, and applications. Presentations on overview, state-of-the-art in research, development, deployment and applications and future trends on satellite networks are assembled