Constellation Program Electrical Ground Support Equipment Research and Development

At the Kennedy Space Center, I engaged in the research and development of electrical ground support equipment for NASA's Constellation Program. Timing characteristics playa crucial role in ground support communications. Latency and jitter are two problems that must be understood so that communications are timely and consistent within the Kennedy Ground Control System (KGCS). I conducted latency and jitter tests using Alien-Bradley programmable logic controllers (PLCs) so that these two intrinsic network properties can be reduced. Time stamping and clock synchronization also play significant roles in launch processing and operations. Using RSLogix 5000 project files and Wireshark network protocol analyzing software, I verified master/slave PLC Ethernet module clock synchronization, master/slave IEEE 1588 communications, and time stamping capabilities. All of the timing and synchronization test results are useful in assessing the current KGCS operational level and determining improvements for the future

Address spaces and virtual memory : specification, implementation, and correctness

In modern operating systems tasks operate concurrently on a logical memory. Address spaces control access rights to and the sharing of that memory. They are associated with tasks and manipulated dynamically by memory management operations of the operating system. For cost reasons, logical memory and address spaces are not implemented directly but simulated. The contents of the logical memory are placed in two different memories, the main and the swap memory. Tasks access their address space by using an architecturally defined address translation mechanism, which is implemented by the memory management unit (MMU) and optimized with a translation look-aside buffer (TLB). This mechanism either redirects a memory access to some main memory location or generates a page fault exception resulting in a call to the page fault handler, a low-level operating system procedure. This construction is correct iff it is transparent to the tasks, so that they behave as if they would operate directly on the logical memory under control of their address spaces. We call the formalization of this correctness criterion a virtual memory simulation theorem. In our thesis we formulate and prove such a theorem for an abstract multiprocessor. We apply the theorem to a concrete implementation, a VAMP [BJK+03] with a singlelevel address translation mechanism and an exemplary page fault handler. We show how to extend the architecture and proofs to support TLBs, multi-level translation, and multiprocessing.In modernen Betriebssystemen operieren Programme nebenläufig auf einem logischen Speicher. Der Zugriff auf diesen Speicher und seine gemeinsame Nutzung wird durch Adressräume geregelt. Diese sind den Programmen zugeordnet und können durch Speicherverwaltungsoperationen des Betriebssystems dynamisch manipuliert werden. Logischer Speicher und Adressräume werden aus Kostengründen nicht direkt implementiert sondern simuliert. Hierbei verteilen sich die Inhalte des logischen Speichers auf zwei verschiedene Speicher, den Haupt- und den Auslagerungsspeicher. Zugriff auf ihren Adressraum wird den Programmen nur unter Nutzung eines durch die Rechnerarchitektur definierten Adressübersetzungsmechanismus gewährt, der durch die Memory Management Unit (MMU) und den Translation Look-Aside Buffer (TLB) implementiert wird. Dieser Mechanismus lenkt einen Zugriff entweder auf eine Hauptspeicheradresse um, oder er erzeugt einen Seitenfehler, der den Aufruf der Seitenfehlerbehandlung, eines hardware-nahen Betriebssystemteils, einleitet. Diese Konstruktion ist korrekt, wenn sie für die Programme transparent ist, das heißt, wenn diese sich mit ihr so verhalten, als griffen sie direkt auf den logischen Speicher unter Kontrolle ihrer Adressräume zu. Die Formalisierung dieser Korrektheitsaussage heißt Simulationssatz für virtuellen Speicher. In der vorliegenden Arbeit formulieren und beweisen wir einen derartigen Satz für ein abstraktes Mehrprozessorsystem. Wir wenden ihn auf eine konkrete Implementierung an, den VAMP [BJK+03] mit einem einstufigen Adressübersetzungsmechanismus und einer exemplarischen Seitenfehlerbehandlung. Wir zeigen, wie Rechnerarchitektur und Korrektheitsbeweise für die Unterstützung von TLBs, mehrstufiger Übersetzung und Mehrprozessorbetrieb erweitert werden können

Short-Packet Communications: Fundamental Performance and Key Enablers

The paradigm shift from 4G to 5G communications, predicted to enable new use cases such as ultra-reliable low-latency communications (URLLC), will enforce a radical change in the design of communication systems. Unlike in 4G systems, where the main objective is to have a large transmission rate, in URLLC, as implied by its name, the objective is to enable transmissions with low latency and, simultaneously, very high reliability. Since low latency implies the use of short data packets, the tension between blocklength and reliability is studied in URLLC.\ua0Several key enablers for URLLC communications have been designated in the literature. A non-exhaustive list contains: multiple transmit and receive antennas (MIMO), short transmission-time intervals (TTI), increased bandwidth, and feedback protocols. Furthermore, it is not only important to introduce additional diversity by means of the above examples, one must also guarantee that the scarce number of channel uses are used in an optimal way. Therefore, protocols for how to convey meta-data such as control information and pilot symbols are needed as are efficient short-packet channel codes.\ua0This thesis focuses on the performance of reliable short-packet communications. Specifically, we provide converse (upper) bounds and achievability (lower) bounds on the maximum coding rate, based on finite-blocklength information theory, for systems that employ the key enablers outlined above. With focus on the Rician and Rayleigh block-fading channels, we are able to answer, e.g., how to optimally utilize spatial and frequency diversity, how far from optimal short-packet channel codes perform, and whether feedback-based schemes are preferable over non-feedback schemes.\ua0More specifically, in Paper A, we study the performance impact of MIMO and a shortened TTI in both uplink and downlink under maximum-likelihood decoding and Rayleigh block-fading. Based on our results, we are able to study the trade-off between bandwidth, latency, spatial diversity, and error probability. Furthermore, we give an example of a pragmatic design of a pilot-assisted channel code that comes within 2.7 dB of our achievability bounds. In Paper B, we partly extend our work in Paper A to the Rician block-fading channel and to practical schemes such as pilot-assisted transmission with nearest neighbor decoding. We derive achievability bounds for pilot-assisted transmission with several different decoders that allow us to quantify the impact, on the achievable performance, of pilots and mismatched decoding. Furthermore, we design short-packet channel codes that perform within 1 dB of our achievability bounds. Paper C contains an achievability bound for a system that employs a variable-length stop-feedback (VLSF) scheme with an error-free feedback link. Based on the results in Paper C and Paper B, we are able to compare non-feedback schemes to stop-feedback schemes and assess if, and when, one is superior to the other. Specifically, we show that, for some practical scenarios, stop-feedback does significantly outperform non-feedback schemes