Thermosonic flip chip interconnection using electroplated copper column arrays

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MICROSTRUCTURAL CHARACTERIZATION AND THERMAL CYCLING RELIABILITY OF SOLDERS UNDER ISOTHERMAL AGING AND ELECTRICAL CURRENT

Solder joints on printed circuit boards provide electrical and mechanical connections between electronic devices and metallized patterns on boards. These solder joints are often the cause of failure in electronic packages. Solders age under storage and operational life conditions, which can include temperature, mechanical loads, and electrical current. Aging occurring at a constant temperature is called isothermal aging. Isothermal aging leads to coarsening of the bulk microstructure and increased interfacial intermetallic compounds at the solder-pad interface. The coarsening of the solder bulk degrades the creep properties of solders, whereas the voiding and brittleness of interfacial intermetallic compounds leads to mechanical weakness of the solder joint. Industry guidelines on solder interconnect reliability test methods recommend preconditioning the solder assemblies by isothermal aging before conducting reliability tests. The guidelines assume that isothermal aging simulates a "reasonable use period," but do not relate the isothermal aging levels with specific use conditions. Studies on the effect of isothermal aging on the thermal cycling reliability of tin-lead and tin-silver-copper solders are limited in scope, and results have been contradictory. The effect of electrical current on solder joints has been has mostly focused on current densities above 104A/cm2 with high ambient temperature (≥100oC), where electromigration, thermomigration, and Joule heating are the dominant failure mechanisms. The effect of current density below 104A/cm2 on temperature cycling fatigue of solders has not been established. This research provides the relation between isothermal aging and the thermal cycling reliability of select Sn-based solders. The Sn-based solders with 3%, 1%, and 0% silver content that have replaced tin-lead are studied and compared against tin-lead solder. The activation energy and growth exponents of the Arrhenius model for the intermetallic growth in the solders are provided. An aging metric to quantify the aging of solder joints, in terms of phase size in the solder bulk and interfacial intermetallic compound thickness at the solder-pad interface, is established. Based on the findings of thermal cycling tests on aged solder assemblies, recommendations are made for isothermal aging of solders before thermal cycling tests. Additionally, the effect of active electrical current at 103 A/cm2 on thermal cycling reliability is reported

Stress-Induced Delamination Of Through Silicon Via Structures

Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady-state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop-up due to interfacial fracture are discussed.Aerospace Engineerin

Numerical modelling of a high temperature power module technology with SiC devices for high density power electronics

This paper presents the development of a new packaging technology using silicon carbide (SiC) power devices. These devices will be used in the next power electronic converters. They will provide higher densities, switching frequencies and operating temperature than current Si technologies. Thus the new designed packaging has to take into account such new constraints. The presented work tries to demonstrate the importance of packaging designs for the performance and reliability of integrated SiC power modules. In order to increase the integrated density in power modules, packaging technologies consisting of two stacked substrates with power devices and copper bumps soldered between them were proposed into two configurations. Silver sintering technique is used as die-attach material solution. In order to assess the assembling process and robustness of these packaging designs, the thermo-mechanical behaviour is studied using FEM modelling. Finally, some recommendations are made in order to choose the suitable design for reliable power module

Modelling of the reliability of flip chip lead-free solder joints at high-temperature excursions

At high-temperature operations of electronic control devices, Tin-Silver-Copper (SnAgCu) alloy solder joints used to assemble the component of the devices are functioning at homologous temperature above 0.8. In such ambient temperatures, solder alloys have limited mechanical strength and will be sensitive to strain rate. The sensitivity of solder properties to creep/visco-plastic deformation increases the rate of accumulation of plastic damage in the alloy and decreases the number of cycles to failure (Nf) of the joints. Most untimely rupture of solder joints in high-temperature electronics (HTE) system usually culminates in colossal loss of resources and lives. Typical incidences are reported in recent automotive and aircraft crashes as well as the collapse of oil-well logging equipment. To increase the mean time to failure (MTTF) of solder joints in HTE, an in-depth understanding and accurate prediction of the response of solder joints to thermally induced plastic strain damage is crucial. This study concerns the prediction of the reliability of lead-free solder joints in a flip chip (FC) model FC48D6.3C457 which is mounted on a substrate and the assembly subjected to high-temperature excursions. The research investigates the effect of the high-temperature operations on reliability of the joints. In addition, the investigation examines the impact of control factors (component stand-off height (CSH), inter-metallic compound (IMC) thickness, number of thermal cycle and solder volume) on Nf of the joints. A model developed in the course of this investigation was employed to create the assembly solder joints architecture. The development of the model and creation of the bump profile involve a combination of both analytical and construction methods. The assembled package on a printed circuit board (PCB) was subjected to accelerated temperature cycle (ATC) employing IEC standard 60749-25 in parts. The cycled temperature range is between -38 oC and 157 oC. Deformation behaviour of SnAgCu alloy solder in the joints is captured using Anand’s visco-plasticity model and the response of other materials in the assembly were simulated with appropriate model. The results demonstrate that the reliability of solder joints operating at elevated temperatures is dependent on CSH, thickness of IMC and solder volume. It also shows that incorporating the IMC layer in the geometric models significantly improves the level of accuracy of fatigue life prediction to ± 22.5% (from the ± 25% which is currently generally accepted). The findings also illustrate that the magnitude of the predicted damage and fatigue life are functions of the number of ATC employed. The extensive set of results from the modelling study has demonstrated the need for incorporating the IMC layer in the geometric model to ensure greater accuracy in the prediction of solder joint service life. The technique developed for incorporating the IMC layer will be of value to R&D engineers and scientists engaged in high-temperature applications in the automotive, aerospace and oil-well logging sectors. The results have been disseminated through peer reviewed journals and also presentations at international conferences

Activity of halide-free flux at copper and tin surfaces

The activity of halogen-free carboxylic acid flux is considered one of the most important aspects in controlling flip chip joint quality recently. In this work, we examined the CuOx removal effectiveness of carboxylic acid solutions at Cu substrates using electrochemical methods at elevated temperatures from 100ºC to 180ºC. Reaction kinetics of CuOx removal were investigated by chronopotentiometry and gravimetric analysis. FTIR was used to study the surface chemistry, and spectrophotometry was used to understand reactant and product solubility. Kinetics of carboxylic acid solution such as adipic acid or maleic acid in polyethylene glycol (PEG) with and without complexing agents such as ethanolamine was investigated. Carboxylic acid-based solutions with ethanolamine show oxide removal rates similar to hydrochloric acid solutions at temperatures above 140ºC. Results indicate the combination of proton-donating complexing agents with carboxylic acids can increase oxide removal rates an order of magnitude over solutions without complexing agents. Sn (II) and Sn (IV) voltammetry shows Sn2+ and Sn4+ can form Sn-carboxylate complex and dissolve into the solution. XPS results indicate under high temperature (180 ºC) and relatively low pH (~2.50), carboxylic acid can clean the surface of Sn as well as halide acid. Equilibrium coefficients between the complexes are obtained and potential-pH diagrams for adipic acid and maleic acid in PEG are presented

Chip-Package Interfacial Stress Analysis and Reliability Implications for Flip-Chip Power Devices

The solder in flip-chip assemblies experience high stress and strain because of thermal mismatch induced deformation. These deformations occur because of the differences of coefficient of thermal expansion between flip-chip assembly materials. The similarly in stress profiles between thermal induced and shear induced stress in solder joints enable the use of die shear testing as a representative technique for relating the max stress the flip-chip can withstand to cyclic thermal fatigue failures. In this work, two electronic device sample preparation types are evaluated: One set of samples are soldered together and other set of samples use epoxy as an adhesive. The soldered samples will have different temperature histories to observe how the max stress is affected by operating environments. For the epoxy samples there will be a sensitivity analysis between the adhesive height and temperature change to conclude what effects solder joint stress more. For solder samples, the temperature history (bake time in oven) decreases the max shear stress in the solder but due to sample limitations, knowing exactly how much is still undetermined. For epoxy samples, as temperature change doubles max interfacial and peeling stress doubles. When gap height doubles interfacial stress decreases by 29.29% and peeling stress decreased by 36.23% (traction free boundary) and 29.74% (periodic boundary)

Fundamental Characterization of Low Dimensional Carbon Nanomaterials for 3D Electronics Packaging

Transistor miniaturization has over the last half century paved the way for higher value electronics every year along an exponential pace known as \u27Moore\u27s law\u27. Now, as the industry is reaching transistor features that no longer makes economic sense, this way of developing integrated circuits (ICs) is coming to its definitive end. As a solution to this problem, the industry is moving toward higher hanging fruits that can enable larger sets of functionalities and ensuring a sustained performance increase to continue delivering more cost-effective ICs every product cycle. These design strategies beyond Moore\u27s law put emphasis on 3D stacking and heterogeneous integration, which if implemented correctly, will deliver a continued development of ICs for a foreseeable future. However, this way of building semiconductor systems does bring new issues to the table as this generation of devices will place additional demands on materials to be successful. The international roadmap of devices and systems (IRDS) highlights the need for improved materials to remove bottlenecks in contemporary as well as future systems in terms of thermal dissipation and interconnect performance. For this very purpose, low dimensional carbon nanomaterials such as graphene and carbon nanotubes (CNTs) are suggested as potential candidates due to their superior thermal, electrical and mechanical properties. Therefore, a successful implementation of these materials will ensure a continued performance to cost development of IC devices.This thesis presents a research study on some fundamental materials growth and reliability aspects of low dimensional carbon based thermal interface materials (TIMs) and interconnects for electronics packaging applications. Novel TIMs and interconnects based on CNT arrays and graphene are fabricated and investigated for their thermal resistance contributions as well electrical performance. The materials are studied and optimized with the support of chemical and structural characterization. Furthermore, a reliability study was performed which found delamination issues in CNT array TIMs due to high strains from thermal expansion mismatches. This study concludes that CNT length is an important factor when designing CNT based systems and the results show that by further interface engineering, reliability can be substantially improved with maintained thermal dissipation and electrical performance. Additionally, a heat treatment study was made that enables improvement of the bulk crystallinity of the materials which will enable even better performance in future applications