716 research outputs found

    Cyclic-Coded Integer-Forcing Equalization

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    A discrete-time intersymbol interference channel with additive Gaussian noise is considered, where only the receiver has knowledge of the channel impulse response. An approach for combining decision-feedback equalization with channel coding is proposed, where decoding precedes the removal of intersymbol interference. This is accomplished by combining the recently proposed integer-forcing equalization approach with cyclic block codes. The channel impulse response is linearly equalized to an integer-valued response. This is then utilized by leveraging the property that a cyclic code is closed under (cyclic) integer-valued convolution. Explicit bounds on the performance of the proposed scheme are also derived

    Integer-Forcing Linear Receivers

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    Linear receivers are often used to reduce the implementation complexity of multiple-antenna systems. In a traditional linear receiver architecture, the receive antennas are used to separate out the codewords sent by each transmit antenna, which can then be decoded individually. Although easy to implement, this approach can be highly suboptimal when the channel matrix is near singular. This paper develops a new linear receiver architecture that uses the receive antennas to create an effective channel matrix with integer-valued entries. Rather than attempting to recover transmitted codewords directly, the decoder recovers integer combinations of the codewords according to the entries of the effective channel matrix. The codewords are all generated using the same linear code which guarantees that these integer combinations are themselves codewords. Provided that the effective channel is full rank, these integer combinations can then be digitally solved for the original codewords. This paper focuses on the special case where there is no coding across transmit antennas and no channel state information at the transmitter(s), which corresponds either to a multi-user uplink scenario or to single-user V-BLAST encoding. In this setting, the proposed integer-forcing linear receiver significantly outperforms conventional linear architectures such as the zero-forcing and linear MMSE receiver. In the high SNR regime, the proposed receiver attains the optimal diversity-multiplexing tradeoff for the standard MIMO channel with no coding across transmit antennas. It is further shown that in an extended MIMO model with interference, the integer-forcing linear receiver achieves the optimal generalized degrees-of-freedom.Comment: 40 pages, 16 figures, to appear in the IEEE Transactions on Information Theor

    Precoded Integer-Forcing Universally Achieves the MIMO Capacity to Within a Constant Gap

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    An open-loop single-user multiple-input multiple-output communication scheme is considered where a transmitter, equipped with multiple antennas, encodes the data into independent streams all taken from the same linear code. The coded streams are then linearly precoded using the encoding matrix of a perfect linear dispersion space-time code. At the receiver side, integer-forcing equalization is applied, followed by standard single-stream decoding. It is shown that this communication architecture achieves the capacity of any Gaussian multiple-input multiple-output channel up to a gap that depends only on the number of transmit antennas.Comment: to appear in the IEEE Transactions on Information Theor

    Spectral Efficiency of MIMO Millimeter-Wave Links with Single-Carrier Modulation for 5G Networks

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    Future wireless networks will extensively rely upon bandwidths centered on carrier frequencies larger than 10GHz. Indeed, recent research has shown that, despite the large path-loss, millimeter wave (mmWave) frequencies can be successfully exploited to transmit very large data-rates over short distances to slowly moving users. Due to hardware complexity and cost constraints, single-carrier modulation schemes, as opposed to the popular multi-carrier schemes, are being considered for use at mmWave frequencies. This paper presents preliminary studies on the achievable spectral efficiency on a wireless MIMO link operating at mmWave in a typical 5G scenario. Two different single-carrier modem schemes are considered, i.e. a traditional modulation scheme with linear equalization at the receiver, and a single-carrier modulation with cyclic prefix, frequency-domain equalization and FFT-based processing at the receiver. Our results show that the former achieves a larger spectral efficiency than the latter. Results also confirm that the spectral efficiency increases with the dimension of the antenna array, as well as that performance gets severely degraded when the link length exceeds 100 meters and the transmit power falls below 0dBW. Nonetheless, mmWave appear to be very suited for providing very large data-rates over short distances.Comment: 8 pages, 8 figures, to appear in Proc. 20th International ITG Workshop on Smart Antennas (WSA2016

    Single-Carrier Modulation versus OFDM for Millimeter-Wave Wireless MIMO

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    This paper presents results on the achievable spectral efficiency and on the energy efficiency for a wireless multiple-input-multiple-output (MIMO) link operating at millimeter wave frequencies (mmWave) in a typical 5G scenario. Two different single-carrier modem schemes are considered, i.e., a traditional modulation scheme with linear equalization at the receiver, and a single-carrier modulation with cyclic prefix, frequency-domain equalization and FFT-based processing at the receiver; these two schemes are compared with a conventional MIMO-OFDM transceiver structure. Our analysis jointly takes into account the peculiar characteristics of MIMO channels at mmWave frequencies, the use of hybrid (analog-digital) pre-coding and post-coding beamformers, the finite cardinality of the modulation structure, and the non-linear behavior of the transmitter power amplifiers. Our results show that the best performance is achieved by single-carrier modulation with time-domain equalization, which exhibits the smallest loss due to the non-linear distortion, and whose performance can be further improved by using advanced equalization schemes. Results also confirm that performance gets severely degraded when the link length exceeds 90-100 meters and the transmit power falls below 0 dBW.Comment: accepted for publication on IEEE Transactions on Communication

    Precoded FIR and Redundant V-BLAST Systems for Frequency-Selective MIMO Channels

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    The vertical Bell labs layered space-time (V-BLAST) system is a multi-input multioutput (MIMO) system designed to achieve good multiplexing gain. In recent literature, a precoder, which exploits channel information, has been added in the V-BLAST transmitter. This precoder forces each symbol stream to have an identical mean square error (MSE). It can be viewed as an alternative to the bit-loading method. In this paper, this precoded V-BLAST system is extended to the case of frequency-selective MIMO channels. Both the FIR and redundant types of transceivers, which use cyclic-prefixing and zero-padding, are considered. A fast algorithm for computing a cyclic-prefixing-based precoded V-BLAST transceiver is developed. Experiments show that the proposed methods with redundancy have better performance than the SVD-based system with optimal powerloading and bit loading for frequency-selective MIMO channels. The gain comes from the fact that the MSE-equalizing precoder has better bit-error rate performance than the optimal bitloading method

    An equalization technique for high rate OFDM systems

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    In a typical orthogonal frequency division multiplexing (OFDM) broadband wireless communication system, a guard interval using cyclic prefix is inserted to avoid the inter-symbol interference and the inter-carrier interference. This guard interval is required to be at least equal to, or longer than the maximum channel delay spread. This method is very simple, but it reduces the transmission efficiency. This efficiency is very low in the communication systems, which inhibit a long channel delay spread with a small number of sub-carriers such as the IEEE 802.11a wireless LAN (WLAN). To increase the transmission efficiency, it is usual that a time domain equalizer (TEQ) is included in an OFDM system to shorten the effective channel impulse response within the guard interval. There are many TEQ algorithms developed for the low rate OFDM applications such as asymmetrical digital subscriber line (ADSL). The drawback of these algorithms is a high computational load. Most of the popular TEQ algorithms are not suitable for the IEEE 802.11a system, a high data rate wireless LAN based on the OFDM technique. In this thesis, a TEQ algorithm based on the minimum mean square error criterion is investigated for the high rate IEEE 802.11a system. This algorithm has a comparatively reduced computational complexity for practical use in the high data rate OFDM systems. In forming the model to design the TEQ, a reduced convolution matrix is exploited to lower the computational complexity. Mathematical analysis and simulation results are provided to show the validity and the advantages of the algorithm. In particular, it is shown that a high performance gain at a data rate of 54Mbps can be obtained with a moderate order of TEQ finite impulse response (FIR) filter. The algorithm is implemented in a field programmable gate array (FPGA). The characteristics and regularities between the elements in matrices are further exploited to reduce the hardware complexity in the matrix multiplication implementation. The optimum TEQ coefficients can be found in less than 4µs for the 7th order of the TEQ FIR filter. This time is the interval of an OFDM symbol in the IEEE 802.11a system. To compensate for the effective channel impulse response, a function block of 64-point radix-4 pipeline fast Fourier transform is implemented in FPGA to perform zero forcing equalization in frequency domain. The offsets between the hardware implementations and the mathematical calculations are provided and analyzed. The system performance loss introduced by the hardware implementation is also tested. Hardware implementation output and simulation results verify that the chips function properly and satisfy the requirements of the system running at a data rate of 54 Mbps
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