An approach for automatic design of application specific instruction set processors (ASIP)

Today‟s hectic world is primarily dominated by electronics. The use of large and hard electronic devices is rapidly being replaced with simple, light and easy-to-carry ones. The past was primarily filled with the notion of performing varied tasks under one roof and the gadgets were built to serve that purpose through the introduction of General Purpose Processors (GPPs) into them. On the contrary, the present tendency is towards devices that are able to perform specific tasks. In the line of this modern concept, the world of embedded system is chiefly dominated by Application Specific Instruction set Processors (ASIPs) because they are geared to perform specific tasks without placing heavy burdens in many respects on the part of the users. Application Specific Instruction set Processors (ASIP), also known as customized processorsare processors designed for particular applications or, for a set of applications.They can be optimized for speed, chip area, and power consumption taking advantage of the flexibility of a synthesized semi-custom implementation. The development of application-specific instruction- set processors is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise in different domains. The main aim of this paper is to propose an approach that will automatically design an ASIP based on the application requirement, which is given as the input to the system. We propose to achieve the same by analyzing different types of RISCMIPS assembly instructions to map the corresponding target VHDL processor to customize maximize the memory access and components of the central processing unit and count the occurrences for the 32-bit RISC CPU based on MIPS. In this work, we also analyze MIPS instruction format, instruction data path, RISC CPU instruction set

Research on Application of Single Chip Microcomputer in Modern Communication System

The application of single chip microcomputer in modern communication system is deeply studied. Firstly, the main types and characteristics of microcontroller are described in detail, including microcontroller classified according to microprocessor architecture, memory type and use environment. Then, it discusses the main application fields of microcontroller in wireless communication, wired communication and optical communication, and analyzes its practical application in these fields. On this basis, the main challenges and problems encountered in modern communication systems are discussed, such as the complexity of design and production, power consumption, compatibility and expansibility. Finally, the solutions to these challenges and problems are put forward, and the future development trend of single-chip microcomputer in modern communication system is discussed

MURAC: A unified machine model for heterogeneous computers

Includes bibliographical referencesHeterogeneous computing enables the performance and energy advantages of multiple distinct processing architectures to be efficiently exploited within a single machine. These systems are capable of delivering large performance increases by matching the applications to architectures that are most suited to them. The Multiple Runtime-reconfigurable Architecture Computer (MURAC) model has been proposed to tackle the problems commonly found in the design and usage of these machines. This model presents a system-level approach that creates a clear separation of concerns between the system implementer and the application developer. The three key concepts that make up the MURAC model are a unified machine model, a unified instruction stream and a unified memory space. A simple programming model built upon these abstractions provides a consistent interface for interacting with the underlying machine to the user application. This programming model simplifies application partitioning between hardware and software and allows the easy integration of different execution models within the single control ow of a mixed-architecture application. The theoretical and practical trade-offs of the proposed model have been explored through the design of several systems. An instruction-accurate system simulator has been developed that supports the simulated execution of mixed-architecture applications. An embedded System-on-Chip implementation has been used to measure the overhead in hardware resources required to support the model, which was found to be minimal. An implementation of the model within an operating system on a tightly-coupled reconfigurable processor platform has been created. This implementation is used to extend the software scheduler to allow for the full support of mixed-architecture applications in a multitasking environment. Different scheduling strategies have been tested using this scheduler for mixed-architecture applications. The design and implementation of these systems has shown that a unified abstraction model for heterogeneous computers provides important usability benefits to system and application designers. These benefits are achieved through a consistent view of the multiple different architectures to the operating system and user applications. This allows them to focus on achieving their performance and efficiency goals by gaining the benefits of different execution models during runtime without the complex implementation details of the system-level synchronisation and coordination

Generation of Customized RISC-V Implementations

Processor customization has become increasingly important for achieving better performance and energy efficiency in embedded systems. However, customizing processors is time-consuming and error-prone work. The design effort is reduced by describing the processor architecture with high-level languages that are then used to generate the processor implementation. In addition to processor customization, open source hardware and standardization have become increasingly more popular. RISC-V that is a relatively new open standard instruction set architecture, has gained traction both in academia and industry. This thesis work added a RISC-V extension to the OpenASIP toolset that is developed at Tampere University. OpenASIP has wide support for customizing and generating transport triggered architectures. Transport triggered architectures have an exposed datapath that is visible to the programmer, which allows a lower level programming interface. The hardware generation and customization features in OpenASIP were reused by utilizing a transport triggered architecture as the internal microarchitecture together with a microcode unit. The extension generates the RISC-V implementations from an architecture description, which reduces the design effort of customizing the implementation. The RISC-V generator developed in this thesis has customization points for the bypass network, amount of pipeline stages, operation latencies and an optional addition of the standard M extension. The generator was evaluated by generating RISC-V cores with different customization points and comparing their performance and post-synthesis properties with open source implementations. The generated cores with bypass network achieved better performance while consuming slightly more area than the smallest reference design. The microcode hardware only utilized 3.6% of the design area and did not affect the maximum clock frequency

Android Application Development for the Intel Platform

Computer scienc

The end of the Intel age

Thesis (S.M. in Engineering and Management)--Massachusetts Institute of Technology, Engineering Systems Division, System Design and Management Program, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 108-111).Executive Summary - The End of the Intel Era. Today, Intel is nearly synonymous with computers. In the past thirty years nearly all personal computers and the great majority of servers have shipped with a processor based on Intel's x86 architecture, of which Intel is the dominant vendor. Yet the past few years have seen a subtle yet remarkable convergence of different industry trends that very well may topple the semiconductor giant. For the past three decades, computers have largely assumed the same shape and form, regardless of their task. Laptops, desktops, and servers have all been based on the same open modular architecture established by IBM. Yet this is not likely to be the case going forward. The past decade has seen the rise of embedded computing, perhaps best epitomized by smartphones and tablet computers. Instead of the standard PC architecture where individual components can be easily exchanged, embedded devices are typically modular designs with highly integrated physical components. Independent functional units, all designed by independent companies, are integrated onto the same piece of silicon to achieve system cost and performance targets. Instead of a standard x86 processor, each device category likely has a chip optimized for its specific application. At the same time that the form of computing is changing, we are witnessing a redistribution of where computing power resides with Cloud Computing and data centers. These have ordinarily been the province of Intel based machines, but data centers have moved from using standard off-the-shelf PCs to custom designed motherboards. Again, we are seeing a shift from the modular personal computer architecture to one that is customized for the task at hand. Another concern for Intel is that the standard metrics by which products compete are in flux. For both embedded systems and data centers, the operational costs and constraints are starting to outweigh the initial outlay costs. An example is the industry shift from overall performance to system power efficiency. Intel has been a relentless driver of processor performance, and this is a significant change of focus for its R&D divisions. Of all Intel's competitors, ARM best represents the magnitude of these challenges for Intel, and is well positioned to take advantage of all these trends. Their business model of licensing their design is well suited for a world with customized architectures, and their extensive experience in low power embedded devices has given them an advantage over Intel in processor power efficiency. Intel is heavily invested in its existing vision of the market. They have always maintained a manufacturing process advantage through tremendous investments in new foundries, and have long championed the open PC modular architecture. Time will ultimately show if Intel is capable of meeting these growing challenges. Yet it is clear that in order to do so, it must make radical changes to itself. One may ask if it is even the same company that emerges.by Robert Swope Fleming.S.M.in Engineering and Managemen

Automatic synthesis of application-specific processors

Thesis (D. Tech. (Engineering: Electrical)) -- Central University of technology, Free State, 2012This thesis describes a method for the automatic generation of appli- cation speci_c processors. The thesis was organized into three sepa- rate but interrelated studies, which together provide: a justi_cation for the method used, a theory that supports the method, and a soft- ware application that realizes the method. The _rst study looked at how modern day microprocessors utilize their hardware resources and it proposed a metric, called core density, for measuring the utilization rate. The core density is a function of the microprocessor's instruction set and the application scheduled to run on that microprocessor. This study concluded that modern day microprocessors use their resources very ine_ciently and proposed the use of subset processors to exe- cute the same applications more e_ciently. The second study sought to provide a theoretical framework for the use of subset processors by developing a generic formal model of computer architecture. To demonstrate the model's versatility, it was used to describe a number of computer architecture components and entire computing systems. The third study describes the development of a set of software tools that enable the automatic generation of application speci_c proces- sors. The FiT toolkit automatically generates a unique Hardware Description Language (HDL) description of a processor based on an application binary _le and a parameterizable template of a generic mi- croprocessor. Area-optimized and performance-optimized custom soft processors were generated using the FiT toolkit and the utilization of the hardware resources by the custom soft processors was character- ized. The FiT toolkit was combined with an ANSI C compiler and a third-party tool for programming _eld-programmable gate arrays (FPGAs) to create an unconstrained C-to-silicon compiler

DESIGN AUTOMATION FOR LOW POWER RFID TAGS

Radio Frequency Identification (RFID) tags are small, wireless devices capable of automated item identification, used in a variety of applications including supply chain management, asset management, automatic toll collection (EZ Pass), etc. However, the design of these types of custom systems using the traditional methods can take months for a hardware engineer to develop and debug. In this dissertation, an automated, low-power flow for the design of RFID tags has been developed, implemented and validated. This dissertation presents the RFID Compiler, which permits high-level design entry using a simple description of the desired primitives and their behavior in ANSI-C. The compiler has different back-ends capable of targeting microprocessor-based or custom hardware-based tags. For the hardware-based tag, the back-end automatically converts the user-supplied behavior in C to low power synthesizable VHDL optimized for RFID applications. The compiler also integrates a fast, high-level power macromodeling flow, which can be used to generate power estimates within 15% accuracy of industry CAD tools and to optimize the primitives and / or the behaviors, compared to conventional practices. Using the RFID Compiler, the user can develop the entire design in a matter of days or weeks. The compiler has been used to implement standards such as ANSI, ISO 18000-7, 18000-6C and 18185-7. The automatically generated tag designs were validated by targeting microprocessors such as the AD Chips EISC and FPGAs such as Xilinx Spartan 3. The corresponding ASIC implementation is comparable to the conventionally designed commercial tags in terms of the energy and area. Thus, the RFID Compiler permits the design of power efficient, custom RFID tags by a wider audience with a dramatically reduced design cycle