79 research outputs found
Low Power Processor Architectures and Contemporary Techniques for Power Optimization โ A Review
The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. ยฉ 2009 ACADEMY PUBLISHER
Practical advances in asynchronous design
Journal ArticleRecent practical advances in asynchronous circuit and system design have resulted in renewed interest by circuit designers. Asynchronous systems are being viewed as in increasingly viable alternative to globally synchronous system organization. This tutorial will present the current state of the art in asynchronous circuit and system design in three different areas. The first section details asynchronous control systems. The second describes a variety of approaches to asynchronous datapaths. The third section is on asynchronous and self-timed circuits applied to the design of general purpose processors
Adaptive Distributed Architectures for Future Semiconductor Technologies.
Year after year semiconductor manufacturing has been able to integrate more components in a single computer chip. These improvements have been possible through systematic shrinking in the size of its basic computational element, the transistor. This trend has allowed computers to progressively become faster, more efficient and less expensive. As this trend continues, experts foresee that current computer designs will face new challenges, in utilizing the minuscule devices made available by future semiconductor technologies. Today's microprocessor designs are not fit to overcome these challenges, since they are constrained by their inability to handle component failures by their lack of adaptability to a wide range of custom modules optimized for specific applications and by their limited design modularity.
The focus of this thesis is to develop original computer architectures, that can not only survive these new challenges, but also leverage the vast number of transistors available to unlock better performance and efficiency. The work explores and evaluates new software and hardware techniques to enable the development of novel adaptive and modular computer designs. The thesis first explores an infrastructure to quantitatively assess the fallacies of current systems and their inadequacy to operate on unreliable silicon. In light of these findings, specific solutions are then proposed to strengthen digital system architectures, both through hardware and software techniques. The thesis culminates with the proposal of a radically new architecture design that can fully adapt dynamically to operate on the hardware resources available on chip, however limited or abundant those may be.PHDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/102405/1/apellegr_1.pd
Increasing rendering performance of graphics hardware
Graphics Processing Unit (GPU) performance is increasing faster than central processing unit (CPU) performance. This growth is driven by performance improvements that can be divided into the following three categories: algorithmic improvements, architectural improvements, and circuit-level improvements. In this dissertation I present techniques that improve the rendering performance of graphics hardware measured in speed, power consumption or image quality in each of these three areas. At the algorithmic level, I introduce a method for using graphics hardware to rapidly and efficiently generate summed-area tables, which are data structures that hold pre-computed two-dimensional integrals of subsets of a given image, and present several novel rendering techniques that take advantage of summed-area tables to produce dynamic, high-quality images at interactive frame rates. These techniques improve the visual quality of images rendered on current commodity GPUs without requiring modifications to the underlying hardware or architecture. At the architectural level, I propose modifications to the architecture of current GPUs that add conditional streaming capabilities. I describe a novel GPU-based ray-tracing algorithm that takes advantage of conditional output streams to reduce the memory bandwidth requirements by over an order of magnitude times when compared to previous techniques. At the circuit level, I propose a compute-on-demand paradigm for the design of high-speed and energy-efficient graphics components. The goal of the compute-on-demand paradigm is to only perform computation at the bit-level when needed. The compute-on-demand paradigm exploits the data-dependent nature of computation, and thereby obtains speed and energy improvements by optimizing designs for the common case. This approach is illustrated with the design of a high-speed Z-comparator that is implemented using asynchronous logic. Asynchronous or "clockless" circuits were chosen for my implementations since they allow for data-dependent completion times and reduced power consumption by disabling inactive components. The resulting circuit-level implementation runs over 1.5 times faster while on dissipating 25% the energy of a comparable synchronous comparator for the average case. Also at the circuit-level, I introduce a novel implementation of counterflow pipelining, which allows two streams of data to flow in opposite directions within the same pipeline without the need for complex arbitration. The advantages of this implementation are demonstrated by the design of a high-speed asynchronous Booth multiplier. While both the comparator and the multiplier are useful components of a graphics pipeline, the objective of this work was to propose the new design paradigm as a promising alternative to current graphics hardware design practices
๊ณต์ ์ค๊ณ ๋ฐ ์ต์ ํ์ ๋ํ ์ํ์ฑ ๊ธฐ๋ฐ ๋ด์ฌ์ ์์ ์ฑ ์ ๊ทผ๋ฒ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ)--์์ธ๋ํ๊ต ๋ํ์ :๊ณต๊ณผ๋ํ ํํ์๋ฌผ๊ณตํ๋ถ,2020. 2. ์ด์ข
๋ฏผ.The role of process safety is to prevent potential disasters in the chemical process. While a variety of techniques are commonly used in the field, accurate risk assessment and analysis require quantitative methods to allow direct comparisons between different alternatives or designs, among other benefits. However, there are various processes with different characteristics and complexities, and not all methods can be equally applied. It is essential to consider safety according to the characteristic of each process and to establish a design method which considers safety from the initial design stage to the operation stage. However, most process safety approaches, such as Quantitative Risk Assessment (QRA) or Hazard and Operability (HAZOP) studies, are conducted at the end of the design process and often have expansive and time-consuming drawbacks due to their repetitive nature. Therefore this thesis proposed a risk-based design method and modeling for designing an inherently safe process to consider the economic feasibility and process safety simultaneously. The thesis deals with elements such as process knowledge management, process safety information, inherently safe design, process hazard analysis for the system configuration required to analyze, and understand the potential risk during the process design and operation. As for the process to apply this, natural gas-related processes, which are recently attracting attention due to the development of shale gas and small and medium-sized gas reservoirs were selected, to determine the optimal design of natural gas liquefaction process. In Chapter 2 of this thesis, the accident models used in the chemical process were analyzed, and the development and validation of the necessary indoor release model were addressed. Chapter 3 covered interactive simulation that uses process data during accident modeling. Finally, Chapter 4 presented a multi-objective optimization methodology to design a safer process by introducing risk modeling and inherent safety. The method is applied to the preliminary design stage of the natural gas liquefaction process and found the result that considers process safety as well as economic feasibility. The limitations of conventional designs using the concept of inherent safety were overcome by implementing the quantitative risk assessment procedure directly in the optimization sequence.ํํ ๊ณต์ ์์ ์ ๊ณต์ ์ ์ํ์ ํ๊ฐํ๊ธฐ ์ํด ์ํ๋๋ค. ์ฌ๋ฌ ๊ธฐ๋ฒ๋ค ์ค ์ผ๋ฐ์ ์ผ๋ก ๊ณต์ ๊ด๋ฆฌ ๋จ๊ณ์์๋ ๋ค์ํ ๊ธฐ๋ฒ์ด ์ฌ์ฉ๋์ง๋ง, ํนํ ๊ณต์ ์์ ์ฑ๊ณผ ์ํ์ฑ์ ์ ํํ๊ฒ ํ๊ฐํ๊ณ ๋ถ์ํ๋ ค๋ฉด ์๋ก ๋ค๋ฅธ ์ค๊ณ๋ ๋์ ๋ฑ๊ณผ ์ง์ ์ ์ธ ๋น๊ต๋ฅผ ๊ฐ๋ฅํ๊ฒ ํ๋ ์ ๋์ ๋ฐฉ๋ฒ์ด ํ์ํ๊ฒ ๋๋ค. ํ์ง๋ง ํน์ฑ๊ณผ ๋ณต์ก์ฑ์ด ๋ค๋ฅธ ๋ค์ํ ๊ณต์ ๋ค์ด ์กด์ฌํ๊ธฐ ๋๋ฌธ์ ๊ฐ ๊ณต์ ์ ํน์ฑ์ ๋ฐ๋ผ ์์ ์ ๊ณ ๋ คํด์ผ ํ๊ณ , ์ด๊ธฐ ์ค๊ณ ๋จ๊ณ๋ถํฐ ์ด์ ๋จ๊ณ๊น์ง ์์ ์ ๊ณ ๋ คํ ํํ ๊ณต์ ์ค๊ณ ๋ฐฉ๋ฒ์ ํ๋ฆฝํ๋ ๊ฒ์ด ์ค์ํ๋ค. ๊ทธ๋ฌ๋ QRA (Quantitative Risk Assessment) ๋๋ HAZOP (Hazard and Operability study) ์ฐ๊ตฌ์ ๊ฐ์ ๋๋ถ๋ถ์ ๊ณต์ ์์ ์ ๊ทผ ๋ฐฉ์์ ์ค๊ณ ์ ์ฐจ ๋ง์ง๋ง์ ๊ณ ๋ ค๋๊ณ , ์ข
์ข
๋ฐ๋ณต์ ์ด๊ฑฐ๋ ์๊ฐ ์๋ชจ์ ์ธ ํน์ฑ์ผ๋ก ์ธํด ๊ธด ์๊ฐ๊ณผ ๋ง์ ๋น์ฉ์ด ๋๋ ๋จ์ ์ด ์กด์ฌํ๋ค. ๋ฐ๋ผ์ ๋ณธ ์ฐ๊ตฌ๋ ๊ณต์ ์ ๊ฒฝ์ ์ ํ๋น์ฑ๊ณผ ์์ ์ฑ์ ๋์์ ๊ณ ๋ คํ๊ธฐ ์ํด ๋ณธ์ง์ ์ผ๋ก ์์ ํ ๊ณต์ ์ ์ค๊ณํ๋ ๊ฒ์ ๋ชฉํ๋ก ํ์ฌ ์ํ ๊ธฐ๋ฐ ์ค๊ณ ๋ฐฉ๋ฒ๊ณผ ์ค๊ณ์ ํ์ํ ๋ชจ๋ธ๋ง์ ์ ์ํ์๋ค. ๋ฐ๋ผ์ ๋ณธ ๋
ผ๋ฌธ์์๋ ๊ณต์ ์ค๊ณ ๋ฐ ์ด์ ์ค์ ๋ฐ์ํ ์ ์๋ ์ํ์ ๋ถ์ํ๊ณ ์ดํดํ๋ ๋ฐ ํ์ํ ์์คํ
๊ตฌ์ฑ์ ์ํด ๊ณต์ ์ง์ ๊ด๋ฆฌ, ๊ณต์ ์์ ์ ๋ณด, ๋ด์ฌ์ ์ผ๋ก ์์ ํ ์ค๊ณ, ๊ณต์ ์ํ ๋ถ์, ํ๋ก์ ํธ ๊ฒฝ์ ์ฑ ๊ฒํ ๋ฑ์ ์์๋ค์ ๋ค๋ฃจ์๋ค. ์ด๋ฅผ ์ ์ฉํ ๊ณต์ ์ผ๋ก๋ ์ต๊ทผ ์
ฐ์ผ ๊ฐ์ค ๋ฐ ์ค์๊ท๋ชจ ๊ฐ์ค์ ๋ฑ์ ๊ฐ๋ฐ๋ก ์ฃผ๋ชฉ ๋ฐ๊ณ ์๋ ์ฒ์ฐ๊ฐ์ค ๊ด๋ จ ๊ณต์ ์ ์ ์ ํ์ฌ ์ต์ข
์ ์ผ๋ก ๋ค๋ชฉ์ ์ต์ ํ๋ฅผ ํตํ LNG ์กํ ๊ณต์ ์ ์ต์ ์ค๊ณ๋ฅผ ๊ฒฐ์ ํ๋ ๊ฒ์ ๋ชฉํ๋ก ํ์๋ค. ๋ณธ ๋
ผ๋ฌธ์ 2์ฅ์์๋ ํํ์ฌ๊ณ ๊ฒฐ๊ณผ ๋ชจ๋ธ๋ง์ ๋ํด ๋ค๋ฃจ์ด ํํ ๊ณต์ ์์ ์ฌ์ฉ๋๋ ๋ชจ๋ธ๋ค์ ๋ํ ๋ถ์์ด ํํด์ก์ผ๋ฉฐ ์ถ๊ฐ๋ก ํ์ํ๋ค๊ณ ๊ณ ๋ ค๋๋ ์ค๋ด ์ ์ถ ๋ชจ๋ธ์ ๋ํ ๊ฐ๋ฐ ๋ฐ ๊ฒ์ฆ์ด ์ ์๋์๋ค. 3์ฅ์์๋ ๊ณต์ ์ ๋ณด๋ฅผ ์ฌ๊ณ ๋ชจ๋ธ๋ง์ ์ฌ์ฉํ๋ ์ธํฐ๋ํฐ๋ธ ์๋ฎฌ๋ ์ด์
์ ๋ํด์ ๋ค๋ฃจ์๋ค. ์ต์ข
์ ์ผ๋ก 4์ฅ์์ ์ด์์ ๊ฒฐ๊ณผ๋ฌผ๋ค์ ์ ์ฉํ์ฌ ๋ณด๋ค ์์ ํ ๊ณต์ ์ ์ค๊ณํ๊ธฐ ์ํ ๋ชฉ์ ์ผ๋ก ๋ด์ฌ์ ์์ ์ฑ์ ๊ฐ๋
์ ๋์
ํ ๋ค๋ชฉ์ ์ต์ ํ ๋ฐฉ๋ฒ๋ก ์ ์ ์ํ์์ผ๋ฉฐ, ์ด๋ฅผ ์ฒ์ฐ๊ฐ์ค ์กํ๊ณต์ ์ ์๋น ์ค๊ณ๋จ๊ณ์ ์ ์ฉํ์ฌ ๊ฒฝ์ ์ฑ๊ณผ ์์ ์ฑ์ ๋์์ ๊ณ ๋ คํ ๊ฒฐ๊ณผ๋ฅผ ์ฐพ์๋๋ค. ์ด ๊ณผ์ ์์ ๊ธฐ์กด ๋ด์ฌ์ ์์ ์ฑ์ ๊ณ ๋ คํ ์ค๊ณ๋ค์ด ๊ฐ์ง๊ณ ์๋ ํ๊ณ๋ฅผ ์ ๋์ ์ํ์ฑ ํ๊ฐ ์ ์ฐจ๋ฅผ ์ต์ ํ ๊ณผ์ ์ ์ง์ ๊ตฌํํ๋ ๊ฒ์ ํตํด ๋ณด์ํ์๋ค.CHAPTER 1. Introduction 1
1.1. Research motivation 1
1.2. Research objective 5
1.3. Outline 6
CHAPTER 2. Accident models in Chemical Process Industries 7
2.1. Introduction 7
2.2. Analysis of conventional accident models for chemical processes 9
2.3. Development of indoor release model 12
2.4. Mitigation effect analysis 35
2.5. Concluding remarks 43
CHAPTER 3. Interactive Process-Accident Simulation 45
3.1. Introduction 45
3.2. Gas pressure regulation station case study 46
3.3. Concluding remarks 53
CHAPTER 4. Process Design with Inherent Safety 54
4.1. Introduction 54
4.2. Process description 61
4.3. Design optimization 68
4.4. Concluding remarks 86
CHAPTER 5. Conclusion 88
Nomenclature 89
References 92
Abstract in Korean (๊ตญ๋ฌธ์ด๋ก) 99Docto
MINIMUM ENERGY DESIGN OF SEAWATER HEAT EXCHANGERS
Industrial cooling with seawater, particularly natural gas liquefaction in arid environments, places large strains on existing heat exchanger designs. High temperature, high salinity water damages metals and leads to devices with a short useful life. Cost effective, corrosion resistant heat exchangers are required to fully utilize available saline water resources. Thermally conductive polymer composites, using carbon fiber fillers to enhance conductivity, are a promising material.
This Thesis provides a characterization, analysis, and optimization of heat exchangers built of anisotropic thermally conductive polymers. The energy content of such polymers is compared to several other materials, and the required content of carbon-fiber fillers is studied for optimum conductivity enhancement. A methodology for the optimization of low thermal conductivity fins, and subsequently heat exchangers, is presented. Finally, the thermal performance of a prototype thermally enhanced polymer heat exchanger is experimentally verified, and compared to numerical and analytical results
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Design and performance optimization of asynchronous networks-on-chip
As digital systems continue to grow in complexity, the design of conventional synchronous systems is facing unprecedented challenges. The number of transistors on individual chips is already in the multi-billion range, and a greatly increasing number of components are being integrated onto a single chip. As a consequence, modern digital designs are under strong time-to-market pressure, and there is a critical need for composable design approaches for large complex systems.
In the past two decades, networks-on-chip (NoCโs) have been a highly active research area. In a NoC-based system, functional blocks are first designed individually and may run at different clock rates. These modules are then connected through a structured network for on-chip global communication. However, due to the rigidity of centrally-clocked NoCโs, there have been bottlenecks of system scalability, energy and performance, which cannot be easily solved with synchronous approaches. As a result, there has been significant recent interest in combing the notion of asynchrony with NoC designs. Since the NoC approach inherently separates the communication infrastructure, and its timing, from computational elements, it is a natural match for an asynchronous paradigm. Asynchronous NoCโs, therefore, enable a modular and extensible system composition for an โobject-orientโ design style.
The thesis aims to significantly advance the state-of-art and viability of asynchronous and globally-asynchronous locally-synchronous (GALS) networks-on-chip, to enable high-performance and low-energy systems. The proposed asynchronous NoCโs are nearly entirely based on standard cells, which eases their integration into industrial design flows. The contributions are instantiated in three different directions.
First, practical acceleration techniques are proposed for optimizing the system latency, in order to break through the latency bottleneck in the memory interfaces of many on-chip parallel processors. Novel asynchronous network protocols are proposed, along with concrete NoC designs. A new concept, called โmonitoring networkโ, is introduced. Monitoring networks are lightweight shadow networks used for fast-forwarding anticipated traffic information, ahead of the actual packet traffic. The routers are therefore allowed to initiate and perform arbitration and channel allocation in advance. The technique is successfully applied to two topologies which belong to two different categories โ a variant mesh-of-trees (MoT) structure and a 2D-mesh topology. Considerable and stable latency improvements are observed across a wide range of traffic patterns, along with moderate throughput gains.
Second, for the first time, a high-performance and low-power asynchronous NoC router is compared directly to a leading commercial synchronous counterpart in an advanced industrial technology. The asynchronous router design shows significant performance improvements, as well as area and power savings. The proposed asynchronous router integrates several advanced techniques, including a low-latency circular FIFO for buffer design, and a novel end-to-end credit-based virtual channel (VC) flow control. In addition, a semi-automated design flow is created, which uses portions of a standard synchronous tool flow.
Finally, a high-performance multi-resource asynchronous arbiter design is developed. This small but important component can be directly used in existing asynchronous NoCโs for performance optimization. In addition, this standalone design promises use in opening up new NoC directions, as well as for general use in parallel systems. In the proposed arbiter design, the allocation of a resource to a client is divided into several steps. Multiple successive client-resource pairs can be selected rapidly in pipelined sequence, and the completion of the assignments can overlap in parallel.
In sum, the thesis provides a set of advanced design solutions for performance optimization of asynchronous and GALS networks-on-chip. These solutions are at different levels, from network protocols, down to router- and component-level optimizations, which can be directly applied to existing basic asynchronous NoC designs to provide a leap in performance improvement
Analysis of low-pressure evaporatively cooled polymer electrolyte membrane fuel cells
The polymer electrolyte membrane fuel cell is being proposed for a number of power
generation systems. With regard to replacing conventional technologies, they offer many
advantages including quiet operation with low emissions. However, the key issue for the
success of fuel cell system will be a superior operational efficiency. The associated subsystems
for controlling fuel cell stack thermal and water management contribute
significantly to the reduction in stack weight and volume and increase the associated
operational parasitic losses. In this thesis a novel fuel cell operational method has been
proposed which utilises a combined humidification and cooling mechanism based on the
direct injection of liquid water to the cathode flow-field. Several analyses were performed
to investigate critical issues for the workable concept of such an EC, or evaporatively
cooled, fuel cell system. [Continues.
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