Antepartum Fetal Monitoring through a Wearable System and a Mobile Application

Prenatal monitoring of Fetal Heart Rate (FHR) is crucial for the prevention of fetal pathologies and unfavorable deliveries. However, the most commonly used Cardiotocographic exam can be performed only in hospital-like structures and requires the supervision of expert personnel. For this reason, a wearable system able to continuously monitor FHR would be a noticeable step towards a personalized and remote pregnancy care. Thanks to textile electrodes, miniaturized electronics, and smart devices like smartphones and tablets, we developed a wearable integrated system for everyday fetal monitoring during the last weeks of pregnancy. Pregnant women at home can use it without the need for any external support by clinicians. The transmission of FHR to a specialized medical center allows its remote analysis, exploiting advanced algorithms running on high-performance hardware able to obtain the best classification of the fetal condition. The system has been tested on a limited set of pregnant women whose fetal electrocardiogram recordings were acquired and classified, yielding an overall score for both accuracy and sensitivity over 90%. This novel approach can open a new perspective on the continuous monitoring of fetus development by enhancing the performance of regular examinations, making treatments really personalized, and reducing hospitalization or ambulatory visits. Keywords: tele-monitoring; wearable devices; fetal heart rate; telemedicin

ASIC based recorders of electrophysiological signals

The ability of application specific integrated circuits (ASICs) to minimise the size and power consumption of electronic circuitry, makes their application to the design of ambulatory monitoring equipment, an attractive option. To this end, a multi-purpose mixed analogue and digital ASIC has been fabricated and incorporated into both a long-term recorder of adult heart rate (HR) and a recorder of electrophysiological signals. The adult HR recorder has been employed in a study of long-term daily HR patterns, which verified the ambulatory nature of this instrument, as well as its suitability for investigating HR variability. The electrophysiological signal recorder uses the ASIC to amplify, filter and digitise signals, which are then stored directly into static RAM. The analogue front-end of this instrument is flexible in terms of gain, bandwidth and sampling frequency allowing it be applied to a whole range of signals. This instrument has been used to record the antepartum fetal HR, as part of the development of an ambulatory, ASIC based recorder of fetal HR (FHR). These recordings have shown that a usable signal can be obtained from a mother in her home environment, whilst in various postures. The electrophysiological signal recorder has also been used to record the electrohysterogram (EHG), which is the name given to the electrical activity of the uterus, from abdominal electrodes during labour. A strong correlation was found to exist between tocographs derived from the EHG and tocographs produced by conventional means

PROCESS AWARE ANALOG-CENTRIC SINGLE LEAD ECG ACQUISITION AND CLASSIFICATION CMOS FRONTEND

The primary objective of this research work is the development of a low power single-lead ECG analog front-end (AFE) architecture which includes acquisition, digitization, process aware efficient gain and frequency control mechanism and a low complexity classifier for the detecting asystole, extreme bardycardia and tachycardia. Recent research on ECG recording systems focuses on the design of a compact single-lead wearable/portable devices with ultra-low-power consumption and in-built hardware for diagnosis and prognosis. Since, the amplitude of the ECG signal varies from hundreds of µV to a few mV, and has a bandwidth of DC to 250 Hz, conventional front-ends use an instrument amplifier followed by a programmable gain amplifier (PGA) to amplify the input ECG signal appropriately. This work presents an mixed signal ECG fronted with an ultra-low power two-stage capacitive-coupled signal conditioning circuit (or an AFE), providing programmable amplification along with tunable 2nd order high pass and lowpass filter characteristics. In the contemporary state-of-the-art ECG recording systems, the gain of the amplifier is controlled by external digital control pins which are in turn dynamically controlled through a DSP. Therefore, an efficient automatic gain control mechanism with minimal area overhead and consuming power in the order of nano watts only. The AGC turns the subsequent ADC on only after output of the PGA (or input of the ADC) reaches a level for which the ADC achieves maximum signal-to-noise-ratio (SNR), hence saving considerable startup power and avoiding the use of DSP. Further, in any practical filter design, the low pass cut-off frequency is prone to deviate from its nominal value across process and temperature variations. Therefore, post-fabrication calibration is essential, before the signal is fed to an ADC, to minimize this deviation, prevent signal degradation due to aliasing of higher frequencies into the bandwidth for classification of ECG signals, to switch to low resolution processing, hence saving power and enhances battery lifetime. Another short-coming noticed in the literature published so far is that the classification algorithm is implemented in digital domain, which turns out to be a power hungry approach. Moreover, Although analog domain implementations of QRS complexes detection schemes have been reported, they employ an external micro-controller to determine the threshold voltage. In this regard, finally a power-efficient low complexity CMOS fully analog classifier architecture and a heart rate estimator is added to the above scheme. It reduces the overall system power consumption by reducing the computational burden on the DSP. The complete proposed scheme consists of (i) an ultra-low power QRS complex detection circuit using an autonomous dynamic threshold voltage, hence discarding the need of any external microcontroller/DSP and calibration (ii) a power efficient analog classifier for the detection of three critical alarm types viz. asystole, extreme bradycardia and tachycardia. Additionally, a heart rate estimator that provides the number of QRS complexes within a period of one minute for cardiac rhythm (CR) and heart rate variability (HRV) analysis. The complete proposed architecture is implemented in UMC 0.18 µm CMOS technology with 1.8 V supply. The functionality of each of the individual blocks are successfully validated using postextraction process corner simulations and through real ECG test signals taken from the PhysioNet database. The capacitive feedback amplifier, Σ∆ ADC, AGC and the AFT are fabricated, and the measurement results are discussed here. The analog classification scheme is successfully validated using embed NXP LPC1768 board, discrete peak detector prototype and FPGA software interfac