Current-Mode Dual-Phase Precision Full-Wave Rectifier Using Current-Mode Two-Cell Winner-Takes-All (WTA) Circuit

In addition to the recently proposed full-wave rectifier by Prommee et al. using voltage-mode (VM)two-cell winner-takes-all (WTA) circuit, we present current-mode (CM) precision full-wave rectifier using CM two-cell WTA circuit. The popular Lazzaro’s CM WTA circuit has been employed for the purpose and there is no requirement of inverting the input signal. Also, dual complimentary phases of the output current signal are available from high-output impedance terminals for explicit utilization. As compared to many recently proposed CM rectifiers using complex active devices, e.g. dual-X current conveyor or universal voltage conveyor, our circuit is very compact and requires a total of 21 transistors. SPICE simulation results of the circuit implemented using 0.35 um TSMC CMOS technology are provided which verify the workability of the proposed circuit

Improving Associative Memory in a Network of Spiking Neurons

In this thesis we use computational neural network models to examine the dynamics and functionality of the CA3 region of the mammalian hippocampus. The emphasis of the project is to investigate how the dynamic control structures provided by inhibitory circuitry and cellular modification may effect the CA3 region during the recall of previously stored information. The CA3 region is commonly thought to work as a recurrent auto-associative neural network due to the neurophysiological characteristics found, such as, recurrent collaterals, strong and sparse synapses from external inputs and plasticity between coactive cells. Associative memory models have been developed using various configurations of mathematical artificial neural networks which were first developed over 40 years ago. Within these models we can store information via changes in the strength of connections between simplified model neurons (two-state). These memories can be recalled when a cue (noisy or partial) is instantiated upon the net. The type of information they can store is quite limited due to restrictions caused by the simplicity of the hard-limiting nodes which are commonly associated with a binary activation threshold. We build a much more biologically plausible model with complex spiking cell models and with realistic synaptic properties between cells. This model is based upon some of the many details we now know of the neuronal circuitry of the CA3 region. We implemented the model in computer software using Neuron and Matlab and tested it by running simulations of storage and recall in the network. By building this model we gain new insights into how different types of neurons, and the complex circuits they form, actually work. The mammalian brain consists of complex resistive-capacative electrical circuitry which is formed by the interconnection of large numbers of neurons. A principal cell type is the pyramidal cell within the cortex, which is the main information processor in our neural networks. Pyramidal cells are surrounded by diverse populations of interneurons which have proportionally smaller numbers compared to the pyramidal cells and these form connections with pyramidal cells and other inhibitory cells. By building detailed computational models of recurrent neural circuitry we explore how these microcircuits of interneurons control the flow of information through pyramidal cells and regulate the efficacy of the network. We also explore the effect of cellular modification due to neuronal activity and the effect of incorporating spatially dependent connectivity on the network during recall of previously stored information. In particular we implement a spiking neural network proposed by Sommer and Wennekers (2001). We consider methods for improving associative memory recall using methods inspired by the work by Graham and Willshaw (1995) where they apply mathematical transforms to an artificial neural network to improve the recall quality within the network. The networks tested contain either 100 or 1000 pyramidal cells with 10% connectivity applied and a partial cue instantiated, and with a global pseudo-inhibition.We investigate three methods. Firstly, applying localised disynaptic inhibition which will proportionalise the excitatory post synaptic potentials and provide a fast acting reversal potential which should help to reduce the variability in signal propagation between cells and provide further inhibition to help synchronise the network activity. Secondly, implementing a persistent sodium channel to the cell body which will act to non-linearise the activation threshold where after a given membrane potential the amplitude of the excitatory postsynaptic potential (EPSP) is boosted to push cells which receive slightly more excitation (most likely high units) over the firing threshold. Finally, implementing spatial characteristics of the dendritic tree will allow a greater probability of a modified synapse existing after 10% random connectivity has been applied throughout the network. We apply spatial characteristics by scaling the conductance weights of excitatory synapses which simulate the loss in potential in synapses found in the outer dendritic regions due to increased resistance. To further increase the biological plausibility of the network we remove the pseudo-inhibition and apply realistic basket cell models with differing configurations for a global inhibitory circuit. The networks are configured with; 1 single basket cell providing feedback inhibition, 10% basket cells providing feedback inhibition where 10 pyramidal cells connect to each basket cell and finally, 100% basket cells providing feedback inhibition. These networks are compared and contrasted for efficacy on recall quality and the effect on the network behaviour. We have found promising results from applying biologically plausible recall strategies and network configurations which suggests the role of inhibition and cellular dynamics are pivotal in learning and memory

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Precizni dvostrani usmerivači malih signala realizovani u tehnici strujnog procesiranja

REZIME: Obrada analognih signala može se izvoditi u tehnici naponskog ili strujnog procesiranja. Iako je naponsko procesiranje imalo dominantniju ulogu u obradi signala dugi niz godina, pojavom strujnih prenosnika, strujno procesiranje dobija na značaju u poslednjih dvadesetak godina zbog više svojih prednosti koje su dokazane na primerima preciznih dvostranih usmerača za male signale obrađenih i u ovoj tezi. Pre svega prednost se ogleda u povećanju širine propusnog opsega zbog upotrebe opterećenja male impedanse. Predmet disertacije je realizacija preciznih dvostranih usmerača za signale malih amplituda u tehnici strujnog procesiranja. Precizno usmeravanje je važna funkcija obrade signala koja ima izuzetnu važnost kod mnogih mernih uređaja kao što su voltmetri i ampermetri za naizmenične signale, detektori polariteta signala, detektori vršne vrednosti, detektori amplitudno-modulisanih signala, kola za usrednjavanje signala itd.. Nakon opisa tehnike strujnog procesiranja i prikaza translinearnog principa, kao polazne osnove za realizaciju brojnih nelinearnih kola u bipolarnoj tehnologiji, razmatran je koncept strujnog prenosnika sa posebnim osvrtom na strujnom prenosniku druge vrste sa bipolarnim tranzistorima. Opisan je i koncept operacionog prenosnika, a sa posebnom pažnjom obrađen je operacioni prenosnik druge vrste sa strujnim kormilarenjem. Dat je i prikaz uporedne analize preciznih dvostranih usmerača realizovanih u tehnici naponskog procesiranja kao i u tehnici strujnog procesiranja, sa prednostima i manama jednih u odnosu na druge. U disertaciji su predstavljena dva modela preciznog dvostranog usmerača za male signale, od kojih prvi model koristi operacioni prenosnik, četiri strujna ogledala i dva strujna izvora, dok je drugi model realizovan sa dva operaciona prenosnika i dve diode sa predpolarizacijom. Osobine realizovanih usmerača su znatno bolje u odnosu na usmerače realizovane sa istim elektronskim komponentam u tehnici naponskog procesiranja. Kroz simulacionu i eksperimentalnu proveru dokazano je da je moguće realizovati precizni dvostrani usmerač u tehnici strujnog procesiranja koji radi u širokom frekventnom opsegu, za signale male amplitude, upotrebom dve diode umesto četiri, kako je to do sada uglavnom rađeno. Takođe je pokazano da ovakav usmerač ima sve bitne osobine bolje od osobina usmerača realizovanog u tehnici naponskog procesiranja.SUMMARY: The processing of analog signals can be performed in the voltage or current processing technique. Although the voltage processing has had a more dominant role in signal processing for many years, with the adventages of current conveyors, current processing has become more important over the past twenty years due to its manifold advantages, which have been proved by examples of precision full wave rectifiers for small signals dealt with in this thesis. The first advantage is the in increase of the bandwidth due to the use of a small impedance load. The subject of the doctoral thesis is the realization of full-wave rectifier for small amplitude signals in a current mode processing techniques. Precise rectification is an important function of signal processing and it is highly significant in many measuring devices, such as voltmeters, ammeters for alternating signals, detectors, signal polarity detectors, peak detectors, amplitude-modulated signal detectors, averaging circuits, etc... The dissertation presents the description of a current processing technique and translinear principle as an initial point for the realization of numerous nonlinear circuits in bipolar technology. This is followed by a speculation on a concept of current conveyor, where a special focus is placed on a different type of current conveyor with bipolar transistors. In addition, the concept of operational conveyor is given with an emphasis on a different type of operational conveyor with current steering output stage. The thesis also presents a comparative analysis of full-wave rectifiers, which are realized in both, voltage and current processing techniques, as well as their advantages and disadvantages compared to each other. The dissertation presents two models of precision full-wave rectifier for low-level signals, as well as the realization of the rectifiers out of which one uses an operational conveyor and four current mirrors and two direct current sources, while another one has two operational conveyors and two diodes with polarization before of them. The characteristics of such rectifiers are significantly better compared to the rectifiers with the same electronic components in voltage processing technique. Through simulation and experimental verification it has been proved that the full-wave rectifier in a current processing technique can be realized for wide frequency range, for low amplitude signals, by using two diodes instead of four, as it has been mostly done so far. It was also shown that such rectifiers have better characteristics than the rectifiers realized in voltage processing mode

Study, Design and Fabrication of an Analogue VLSI Ormia-Ochracea-Inspired Delay Magnification System

This Thesis entails the development of a low-power delay magnification system inspired by the mechanical structure of the ear of the parasitoid fly Ormia Ochracea (O2). The proposed system is suitable as a preprocessing unit for binaural sound localization processors equipped with miniature acoustic sensors. The core of the Thesis involves the study of a delay magnification system based on the O2 sound localization mechanism and the design and testing of a low-power analog integrated circuit based on a proposed, novel delay magnification system inspired by Ormia Ochracea. The study of the delay magnification system based on the O2 sound localization mechanism is divided into two main parts. The first part studies in detail the delay magnification mechanism of the O2 ears. This study sheds light and tries to comprehend what mechanical parameters of the O2 ears are involved in the delay magnification process and how these parameters contribute to the magnification of the delay. The study presents the signal-flow-graph of the O2 system which can be used as a generic delay magnification model for the O2 ears. We also explore the effects of the tuning of the O2 system parameters on the output interaural time difference (ITD). Inspired by the study of the O2 system, in the second part of our study, we modify the O2 system using simpler building blocks and structure which can provide a delay magnification comparable to the original O2 system. We present a new binaural sound localization system suitable for small ITDs which utilizes the new modified O2 system, cochlea filter banks, cross-correlograms and our re-mapping algorithm and show that it can be used to encode very small input delay values that could not be resolved by means of a conventional binaural processor based on the Jeffress’s coincidence detection model. We evaluate the sound localization performance of our new binaural sound localization system for a single sound source and a sound source in the presence of a competing sound source scenario through detailed simulation. The performance of the proposed system is also explored in the presence of filter bandwidth variation and cochlea filter mismatch. After the study of the O2 delay magnification system, we present an analog VLSI chip which morphs the O2 delay magnification system. To determine what topology is the best morphing platform for the O2 system, we present the design and comparative performance of the O2 system when log-domain and gm-C second order weak-inversion filters are employed. The design of the proposed low-power modified O2 system circuit based on translinear loops is detailed. Its performance is evaluated through detailed simulation. Subsequently the Thesis proceeds with the design, fabrication and testing of the new chip based on the modified O2 circuit. The synthesis and testing of the proposed circuit using 0.35μm AMS CMOS process technology parameters is discussed. Detailed measured results confirm the delay magnification ability of the modified O2 circuit and its compliance with theoretical analysis explained earlier in the Thesis. The fabricated system is tuned to operate in the 100Hz to 1kHz frequency range, is able to achieve a delay gain of approximately 3.5 to 9.5 when the input (physical) delay ranges from 0μs to 20μs, and consumes 13.1μW with a 2 V power supply

Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing

Human society is now facing grand challenges to satisfy the growing demand for computing power, at the same time, sustain energy consumption. By the end of CMOS technology scaling, innovations are required to tackle the challenges in a radically different way. Inspired by the emerging understanding of the computing occurring in a brain and nanotechnology-enabled biological plausible synaptic plasticity, neuromorphic computing architectures are being investigated. Such a neuromorphic chip that combines CMOS analog spiking neurons and nanoscale resistive random-access memory (RRAM) using as electronics synapses can provide massive neural network parallelism, high density and online learning capability, and hence, paves the path towards a promising solution to future energy-efficient real-time computing systems. However, existing silicon neuron approaches are designed to faithfully reproduce biological neuron dynamics, and hence they are incompatible with the RRAM synapses, or require extensive peripheral circuitry to modulate a synapse, and are thus deficient in learning capability. As a result, they eliminate most of the density advantages gained by the adoption of nanoscale devices, and fail to realize a functional computing system. This dissertation describes novel hardware architectures and neuron circuit designs that synergistically assemble the fundamental and significant elements for brain-inspired computing. Versatile CMOS spiking neurons that combine integrate-and-fire, passive dense RRAM synapses drive capability, dynamic biasing for adaptive power consumption, in situ spike-timing dependent plasticity (STDP) and competitive learning in compact integrated circuit modules are presented. Real-world pattern learning and recognition tasks using the proposed architecture were demonstrated with circuit-level simulations. A test chip was implemented and fabricated to verify the proposed CMOS neuron and hardware architecture, and the subsequent chip measurement results successfully proved the idea. The work described in this dissertation realizes a key building block for large-scale integration of spiking neural network hardware, and then, serves as a step-stone for the building of next-generation energy-efficient brain-inspired cognitive computing systems

Prefrontal rhythms for cognitive control

Goal-directed behavior requires flexible selection among action plans and updating behavioral strategies when they fail to achieve desired goals. Lateral prefrontal cortex (LPFC) is implicated in the execution of behavior-guiding rule-based cognitive control while anterior cingulate cortex (ACC) is implicated in monitoring processes and updating rules. Rule-based cognitive control requires selective processing while process monitoring benefits from combinatorial processing. I used a combination of computational and experimental methods to investigate how network oscillations and neuronal heterogeneity contribute to cognitive control through their effects on selective versus combinatorial processing modes in LPFC and ACC. First, I adapted an existing LPFC model to explore input frequency- and coherence-based output selection mechanisms for flexible routing of rate-coded signals. I show that the oscillatory states of input encoding populations can exhibit a stronger influence over downstream competition than their activity levels. This enables an output driven by a weaker resonant input signal to suppress lower-frequency competing responses to stronger, less resonant (though possibly higher-frequency) input signals. While signals are encoded in population firing rates, output selection and signal routing can be governed independently by the frequency and coherence of oscillatory inputs and their correspondence with output resonant properties. Flexible response selection and gating can be achieved by oscillatory state control mechanisms operating on input encoding populations. These dynamic mechanisms enable experimentally-observed LPFC beta and gamma oscillations to flexibly govern the selection and gating of rate-coded signals for downstream read-out. Furthermore, I demonstrate how differential drives to distinct interneuron populations can switch working memory representations between asynchronous and oscillatory states that support rule-based selection. Next, I analyzed physiological data from the LeBeau laboratory and built a de novo model constrained by the biological data. Experimental data demonstrated that fast network oscillations at both the beta- and gamma frequency bands could be elicited in vitro in ACC and neurons exhibited a wide range of intrinsic properties. Computational modeling of the ACC network revealed that the frequency of network oscillation generated was dependent upon the time course of inhibition. Principal cell heterogeneity broadened the range of frequencies generated by the model network. In addition, with different frequency inputs to two neuronal assemblies, heterogeneity decreased competition and increased spike coherence between the networks thus conferring a combinatorial advantage to the network. These findings suggest that oscillating neuronal populations can support either response selection (routing), or combination, depending on the interplay between the kinetics of synaptic inhibition and the degree of heterogeneity of principal cell intrinsic conductances. Such differences may support functional differences between the roles of LPFC and ACC in cognitive control

Efficient audio signal processing for embedded systems

We investigated two design strategies that would allow us to efficiently process audio signals on embedded systems such as mobile phones and portable electronics. In the first strategy, we exploit properties of the human auditory system to process audio signals. We designed a sound enhancement algorithm to make piezoelectric loudspeakers sound "richer" and "fuller," using a combination of bass extension and dynamic range compression. We also developed an audio energy reduction algorithm for loudspeaker power management by suppressing signal energy below the masking threshold. In the second strategy, we use low-power analog circuits to process the signal before digitizing it. We designed an analog front-end for sound detection and implemented it on a field programmable analog array (FPAA). The sound classifier front-end can be used in a wide range of applications because programmable floating-gate transistors are employed to store classifier weights. Moreover, we incorporated a feature selection algorithm to simplify the analog front-end. A machine learning algorithm AdaBoost is used to select the most relevant features for a particular sound detection application. We also designed the circuits to implement the AdaBoost-based analog classifier.PhDCommittee Chair: Anderson, David; Committee Member: Hasler, Jennifer; Committee Member: Hunt, William; Committee Member: Lanterman, Aaron; Committee Member: Minch, Bradle

cAMP-dependent regulation of HCN4 controls the tonic entrainment process in sinoatrial node pacemaker cells

It is highly debated how cyclic adenosine monophosphate-dependent regulation (CDR) of the major pacemaker channel HCN4 in the sinoatrial node (SAN) is involved in heart rate regulation by the autonomic nervous system. We addressed this question using a knockin mouse line expressing cyclic adenosine monophosphate-insensitive HCN4 channels. This mouse line displayed a complex cardiac phenotype characterized by sinus dysrhythmia, severe sinus bradycardia, sinus pauses and chronotropic incompetence. Furthermore, the absence of CDR leads to inappropriately enhanced heart rate responses of the SAN to vagal nerve activity in vivo. The mechanism underlying these symptoms can be explained by the presence of nonfiring pacemaker cells. We provide evidence that a tonic and mutual interaction process (tonic entrainment) between firing and nonfiring cells slows down the overall rhythm of the SAN. Most importantly, we show that the proportion of firing cells can be increased by CDR of HCN4 to efficiently oppose enhanced responses to vagal activity. In conclusion, we provide evidence for a novel role of CDR of HCN4 for the central pacemaker process in the sinoatrial node. The involvement of cAMP-dependent regulation of HCN4 in the chronotropic heart rate response is a matter of debate. Here the authors use a knockin mouse model expressing cAMP-insensitive HCN4 channels to discover an inhibitory nonfiring cell pool in the sinoatrial node and a tonic and mutual interaction between firing and nonfiring pacemaker cells that is controlled by cAMP-dependent regulation of HCN4, with implications in chronotropic heart rate responses