17,850 research outputs found
Memcapacitive Devices in Logic and Crossbar Applications
Over the last decade, memristive devices have been widely adopted in
computing for various conventional and unconventional applications. While the
integration density, memory property, and nonlinear characteristics have many
benefits, reducing the energy consumption is limited by the resistive nature of
the devices. Memcapacitors would address that limitation while still having all
the benefits of memristors. Recent work has shown that with adjusted parameters
during the fabrication process, a metal-oxide device can indeed exhibit a
memcapacitive behavior. We introduce novel memcapacitive logic gates and
memcapacitive crossbar classifiers as a proof of concept that such applications
can outperform memristor-based architectures. The results illustrate that,
compared to memristive logic gates, our memcapacitive gates consume about 7x
less power. The memcapacitive crossbar classifier achieves similar
classification performance but reduces the power consumption by a factor of
about 1,500x for the MNIST dataset and a factor of about 1,000x for the
CIFAR-10 dataset compared to a memristive crossbar. Our simulation results
demonstrate that memcapacitive devices have great potential for both Boolean
logic and analog low-power applications
A 2.5MHz 55dB Switched-Current BandPass ΣΔ Modulator for AM Signal Conversion.
We present a Switched-Current (SI) fourth-order bandpass ΣΔ modulator IC prototype. It uses fully-differential circuits in 0.8μm CMOS technology to obtain a Dynamic Range (DR) larger than 55dB at 2.5MHz center frequency with 30kHz bandwidth - in accordance to the requirements of AM digital receivers. The prototype incorporates a single-ended to fully-differential current-mode buffer for testing purposes. The power consumption of the whole prototype (modulator plus buffer) is 60mW from a 5V supply voltage.This work has been supported by the European Union, under ESPRIT Project 8795-AMFIS.Peer reviewe
Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition
A neuromorphic chip that combines CMOS analog spiking neurons and memristive
synapses offers a promising solution to brain-inspired computing, as it can
provide massive neural network parallelism and density. Previous hybrid analog
CMOS-memristor approaches required extensive CMOS circuitry for training, and
thus eliminated most of the density advantages gained by the adoption of
memristor synapses. Further, they used different waveforms for pre and
post-synaptic spikes that added undesirable circuit overhead. Here we describe
a hardware architecture that can feature a large number of memristor synapses
to learn real-world patterns. We present a versatile CMOS neuron that combines
integrate-and-fire behavior, drives passive memristors and implements
competitive learning in a compact circuit module, and enables in-situ
plasticity in the memristor synapses. We demonstrate handwritten-digits
recognition using the proposed architecture using transistor-level circuit
simulations. As the described neuromorphic architecture is homogeneous, it
realizes a fundamental building block for large-scale energy-efficient
brain-inspired silicon chips that could lead to next-generation cognitive
computing.Comment: This is a preprint of an article accepted for publication in IEEE
Journal on Emerging and Selected Topics in Circuits and Systems, vol 5, no.
2, June 201
Digital Offset Calibration of an OPAMP Towards Improving Static Parameters of 90 nm CMOS DAC
In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90 nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error is achieved
Low-power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator
We present a novel driver circuit enabling electro-optic modulation with high extinction ratio from a co-designed silicon ring modulator. The driver circuit provides an asymmetric differential output at 10Gbps with a voltage swing up to 1.5V(pp) from a single 1.0V supply, maximizing the resonance-wavelength shift of depletion-type ring modulators while avoiding carrier injection. A test chip containing 4 reconfigurable driver circuits was fabricated in 40nm CMOS technology. The measured energy consumption for driving a 100fF capacitive load at 10Gbps was as low as 125fJ/bit and 220fJ/bit at 1V(pp) and 1.5V(pp) respectively. After flip-chip integration with ring modulators on a silicon-photonics chip, the power consumption was measured to be 210fJ/bit and 350fJ/bit respectively
Realization of a ROIC for 72x4 PV-IR detectors
Silicon Readout Integrated Circuits (ROIC) for HgCdTe Focal Plane Arrays of 1x4 and 72x4 photovoltaic detectors are represented. The analog circuit blocks are completely identical for both, while the digital control circuit is modified to
take into account the larger array size. The manufacturing technology is 0.35μm, double poly-Si, three-metal CMOS process. ROIC structure includes four elements TDI functioning with a super sampling rate of 3, bidirectional scanning, dead pixel de-selection, automatic gain adjustment in response to pixel deselection besides programmable four gain setting (up to 2.58pC storage), and programmable integration time. ROIC has four outputs with a dynamic range of 2.8V (from 1.2V to 4V) for an output load of 10pF capacitive in parallel with 1MΩ resistance, and operates at a clock frequency of 5 MHz. The input referred noise is less than 1037 μV with 460 fF integration capacitor, corresponding to 2978 electrons
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