608 research outputs found
Electronic equipment, systems, and techniques: A compilation
Electronic circuits with specialized computer applications and control circuits are presented. Patent information is included
Novel active function blocks and their applications in frequency filters and quadrature oscillators
KmitoÄtovĂ© filtry a sinusoidnĂ oscilĂĄtory jsou lineĂĄrnĂ elektronickĂ© obvody, kterĂ© jsou pouĆŸĂvĂĄny v ĆĄirokĂ© oblasti elektroniky a jsou zĂĄkladnĂmi stavebnĂmi bloky v analogovĂ©m zpracovĂĄnĂ signĂĄlu. V poslednĂ dekĂĄdÄ pro tento ĂșÄel bylo prezentovĂĄno velkĂ© mnoĆŸstvĂ stavebnĂch funkÄnĂch blokĆŻ. V letech 2000 a 2006 na Ăstavu telekomunikacĂ, VUT v BrnÄ byly definovĂĄny univerzĂĄlnĂ proudovĂœ konvejor (UCC) a univerzĂĄlnĂ napÄt'ovĂœ konvejor (UVC) a vyrobeny ve spoluprĂĄci s firmou AMI Semiconductor Czech, Ltd. OvĆĄem, stĂĄle existuje poĆŸadavek na vĂœvoj novĂœch aktivnĂch prvkĆŻ, kterĂ© nabĂzejĂ novĂ© vĂœhody. HlavnĂ pĆĂnos prĂĄce proto spoÄĂvĂĄ v definici dalĆĄĂch pĆŻvodnĂch aktivnĂch stavebnĂch blokĆŻ jako jsou differential-input buffered and transconductance amplifier (DBTA), current follower transconductance amplifier (CFTA), z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), generalized current follower differential input transconductance amplifier (GCFDITA), voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), a minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). PomocĂ navrĆŸenĂœch aktivnĂch stavebnĂch blokĆŻ byly prezentovĂĄny pĆŻvodnĂ zapojenĂ fĂĄzovacĂch ÄlĂĄnkĆŻ prvnĂho ĆĂĄdu, univerzĂĄlnĂ filtry druhĂ©ho ĆĂĄdu, ekvivalenty obvodu typu KHN, inverznĂ filtry, aktivnĂ simulĂĄtory uzemnÄnĂ©ho induktoru a kvadraturnĂ sinusoidnĂ oscilĂĄtory pracujĂcĂ v proudovĂ©m, napÄt'ovĂ©m a smĂĆĄenĂ©m mĂłdu. ChovĂĄnĂ navrĆŸenĂœch obvodĆŻ byla ovÄĆena simulacĂ v prostĆedĂ SPICE a ve vybranĂœch pĆĂpadech experimentĂĄlnĂm mÄĆenĂm.Frequency filters and sinusoidal oscillators are linear electric circuits that are used in wide area of electronics and also are the basic building blocks in analogue signal processing. In the last decade, huge number of active building blocks (ABBs) were presented for this purpose. In 2000 and 2006, the universal current conveyor (UCC) and the universal voltage conveyor (UVC), respectively, were designed at the Department of Telecommunication, BUT, Brno, and produced in cooperation with AMI Semiconductor Czech, Ltd. There is still the need to develop new active elements that offer new advantages. The main contribution of this thesis is, therefore, the definition of other novel ABBs such as the differential-input buffered and transconductance amplifier (DBTA), the current follower transconductance amplifier (CFTA), the z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), the generalized current follower differential input transconductance amplifier (GCFDITA), the voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), and the minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). Using the proposed ABBs, novel structures of first-order all-pass filters, second-order universal filters, KHN-equivalent circuits, inverse filters, active grounded inductance simulators, and quadrature sinusoidal oscillators working in the current-, voltage-, or mixed-mode are presented. The behavior of the proposed circuits has been verified by SPICE simulations and in selected cases also by experimental measurements.
Equalizer State Caching for Fast Data Recovery in Optically-Switched Data Center Networks
Optical switching offers the potential to significantly
scale the capacity of data center networks (DCN) with a
simultaneous reduction in switching time and power consumption.
Previous research has shown that end-to-end switching time,
which is the sum of the switch configuration time and the clock
and data recovery (CDR) locking time, should be kept within a few
nanoseconds for high network throughput. This challenge of low
switching time has motivated research into fast optical switches,
ultra-fast clock and amplitude recovery techniques. Concurrently,
the data rate between server-to-server and server-to-switch
interconnect is increasing drastically from the current 100 Gb/s
(4Ă25 Gb/s) to 400 Gb/s and beyond, motivating the use of high
order formats such as 50-GBaud four-level pulse-amplitude
modulation (PAM-4) for signalling. Since PAM-4 is more sensitive
to noise and distortion, digital equalizers are generally needed to
compensate for impairments such as transceiver frequency rolloff, dispersion and optical filtering, adding additional time for
equalizer adaptation and power consumption that are undesired
for fast optical switching systems. Here we propose and investigate
an equalizer state caching technique that reduces equalizer
adaptation time and computation power consumption for fast
optical switching systems, underpinning optically-switched DCNs
using high baud rate and impairment-sensitive formats. Through
a proof-of-concept experiment, we study the performance of the
proposed equalizer state caching scheme in a three-node optical
switching system using 56 GBaud PAM-4. Our experimental
results show that the proposed scheme can tolerate up to 0.8-nm
(100-GHz) instantaneous wavelength change with an adaptation
delay of only 0.36 ns. Practical considerations such as clock phase
misalignment, temperature-induced wavelength drift, and
equalizer precision are also studied
High-speed equalization and transmission in electrical interconnections
The relentless growth of data traffic and increasing digital signal processing capabilities of integrated circuits (IC) are demanding ever faster chip-to-chip / chip-to-module serial electrical interconnects. As data rates increase, the signal quality after transmission over printed circuit board (PCB) interconnections is severely impaired. Frequency-dependent loss and crosstalk noise lead to a reduced eye opening, a reduced signal-to-noise ratio and an increased inter-symbol interference (ISI). This, in turn, requires the use of improved signal processing or PCB materials, in order to overcome the bandwidth (BW) limitations and to improve signal integrity. By applying an optimal combination of equalizer and receiver electronics together with BW-efficient modulation schemes, the transmission rate over serial electrical interconnections can be pushed further. At the start of this research, most industrial backplane connectors, meeting the IEEE and OIF specifications such as manufactured by e.g. FCI or TE connectivity, had operational capabilities of up to 25 Gb/s.
This research was mainly performed under the IWT ShortTrack project.
The goal of this research was to increase the transmission speed over electrical backplanes up to 100 Gb/s per channel for next-generation telecom systems and data centers. This requirement greatly surpassed the state-ofthe-art reported in previous publications, considering e.g. 25 Gb/s duobinary and 42.8 Gb/s PAM-4 transmission over a low-loss Megtron 6 electrical backplane using off-line processing.
The successful implementation of the integrated transmitter (TX) and receiver (RX) (1) , clearly shows the feasibility of single lane interconnections beyond 80 Gb/s and opens the potential of realizing industrial 100 Gb/s links using a recent IC technology process. Besides the advancement of the state-of-the-art in the field of high-speed transceivers and backplane transmission systems, which led to several academic publications, the output of this work also attracts a lot of attention from the industry, showing the potential to commercialize the developed chipset and technologies used in this research for various applications: not only in high-speed electrical transmission links, but also in high-speed opto-electronic communications such as access, active optical cables and optical backplanes.
In this dissertation, the background of this research, an overview of this work and the thesis organization are illustrated in Chapter 1.
In Chapter 2, a system level analysis is presented, showing that the channel losses are limiting the transmission speed over backplanes. In order to enhance the serial data rate over backplanes and to eliminate the signal degradation, several technologies are discussed, such as signal equalization and modulation techniques. First, a prototype backplane channel, from project partner FCI, implemented with improved backplane connectors is characterized. Second, an integrated transversal filter as a feed-forward equalizer (FFE) is selected to perform the signal equalization, based on a comprehensive consideration of the backplane channel performance, equalization capabilities, implementation complexity and overall power consumption. NRZ, duobinary and PAM-4 are the three most common modulation schemes for ultra-high speed electrical backplane communication. After a system-level simulation and comparison, the duobinary format is selected due to its high BW efficiency and reasonable circuit complexity. Last, different IC technology processes are compared and the ST microelectronics BiCMOS9MW process (featuring a fT value of over 200 GHz) is selected, based on a trade-off between speed and chip cost. Meanwhile it also has a benefit for providing an integrated microstrip model, which is utilized for the delay elements of the FFE.
Chapter 3 illustrates the chip design of the high-speed backplane TX, consisting of a multiplexer (MUX) and a 5-tap FFE. The 4:1 MUX combines four lower rate streams into a high-speed differential NRZ signal up to 100 Gb/s as the FFE input. The 5-tap FFE is implemented with a novel topology for improved testability, such that the FFE performance can be individually characterized, in both frequency- and time-domain, which also helps to perform the coefficient optimization of the FFE. Different configurations for the gain cell in the FFE are compared. The gilbert configuration shows most advantages, in both a good high-frequency performance and an easy way to implement positive / negative amplification. The total chip, including the MUX and the FFE, consumes 750mW from a 2.5V supply and occupies an area of 4.4mm Ă 1.4 mm.
In Chapter 4, the TX chip is demonstrated up to 84 Gb/s. First, the FFE performance is characterized in the frequency domain, showing that the FFE is able to work up to 84 Gb/s using duobinary formats. Second, the combination of the MUX and the FFE is tested. The equalized TX outputs are captured after different channels, for both NRZ and duobinary signaling at speeds from 64 Gb/s to 84 Gb/s. Then, by applying the duobinary RX 2, a serial electrical transmission link is demonstrated across a pair of 10 cm coax cables and across a 5 cm FX-2 differential stripline. The 5-tap FFE compensates a total loss between the TX and the RX chips of about 13.5 dB at the Nyquist frequency, while the RX receives the equalized signal and decodes the duobinary signal to 4 quarter rate NRZ streams. This shows a chip-to-chip data link with a bit error rate (BER) lower than 10â11.
Last, the electrical data transmission between the TX and the RX over two commercial backplanes is demonstrated. An error-free, serial duobinary transmission across a commercial Megtron 6, 11.5 inch backplane is demonstrated at 48 Gb/s, which indicates that duobinary outperforms NRZ for attaining higher speed or longer reach backplane applications. Later on, using an ExaMAXÂź backplane demonstrator, duobinary transmission performance is verified and the maximum allowed channel loss at 40 Gb/s transmission is explored. The eye diagram and BER measurements over a backplane channel up to 26.25 inch are performed. The results show that at 40 Gb/s, a total channel loss up to 37 dB at the Nyquist frequency allows for error-free duobinary transmission, while a total channel loss of 42 dB was overcome with a BER below 10â8.
An overview of the conclusions is summarized in Chapter 5, along with some suggestions for further research in this field.
(1) The duobinary receiver was developed by my colleague Timothy De Keulenaer, as described in his PhD dissertation.
(2) Described in the PhD dissertation of Timothy De Keulenaer
Voltage Type First Order All-Pass Filter Employing Fully Differential Current Feedback Operational Amplifier and Quadrature Oscillator
DergiPark: 245968trakyafbdAn improvement voltage mode first order all-pass filter configuration is proposed. The presented circuit uses a single fully differential current feedback operational amplifier (FDCFOA), resistors and a grounded capacitor. High input impedance of the proposed filter enables the circuit to be cascaded without additional buffers. It does not impose any component matching constraint in analog signal processing circuits. Also higher order all-pass filter could be achieved by cascading the proposed all-pass sections. In order to demostrate the performance of the proposed filter a new voltage mode oscillator is introduced as an application example. Furthermore the theoretical results are verified with SPICE simulations using a CMOS realization of FDCFOAGerilim modunda birinci dereceden tĂŒm geçiren yeni bir sĂŒzgeç devresi önerilmiĆtir. Ănerilen devrede bir tam diferansiyel akım geribeslemeli iĆlemsel kuvvetlendirici, dirençler ve topraklı bir kapasite bulunmaktadır. Ănerilen devrenin yĂŒksek giriĆ direnci, ek tampon kullanılmadan devrenin kaskad baÄlanabilmesini saÄlamaktadır. Analog iĆaret iĆleme devrelerinde herhangi bir eleman denkleĆtirme koĆuluna gerek duyulmamaktadır. Aynı zamanda daha yĂŒksek dereceden tĂŒm geçiren sĂŒzgeçler önerilen birinci dereceden sĂŒzgeçler kaskad baÄlanarak elde edilebilmektedir. Ănerilen sĂŒzgecin baĆarımını göstermek amacıyla, bir uygulama örneÄi olarak gerilim modunda yeni bir osilatör tanıtılmıĆtır. Bundan baĆka teorik sonuçlar, FDCFOA elemanının CMOS gerçeklenmesi kullanılarak SPICE benzetimleriyle doÄrulanmıĆtır
An Overview on Application of Machine Learning Techniques in Optical Networks
Today's telecommunication networks have become sources of enormous amounts of
widely heterogeneous data. This information can be retrieved from network
traffic traces, network alarms, signal quality indicators, users' behavioral
data, etc. Advanced mathematical tools are required to extract meaningful
information from these data and take decisions pertaining to the proper
functioning of the networks from the network-generated data. Among these
mathematical tools, Machine Learning (ML) is regarded as one of the most
promising methodological approaches to perform network-data analysis and enable
automated network self-configuration and fault management. The adoption of ML
techniques in the field of optical communication networks is motivated by the
unprecedented growth of network complexity faced by optical networks in the
last few years. Such complexity increase is due to the introduction of a huge
number of adjustable and interdependent system parameters (e.g., routing
configurations, modulation format, symbol rate, coding schemes, etc.) that are
enabled by the usage of coherent transmission/reception technologies, advanced
digital signal processing and compensation of nonlinear effects in optical
fiber propagation. In this paper we provide an overview of the application of
ML to optical communications and networking. We classify and survey relevant
literature dealing with the topic, and we also provide an introductory tutorial
on ML for researchers and practitioners interested in this field. Although a
good number of research papers have recently appeared, the application of ML to
optical networks is still in its infancy: to stimulate further work in this
area, we conclude the paper proposing new possible research directions
Programming of a led matrix with a digital vu meter application
[EN] In this project I want to develop an application for a 16*16 LED Matrix. Itâs composed of 256 RGB 5050 programmable LEDs, in concrete the ws2812b LED. The idea is to use an Arduino board (microcontroller) to control the LED Matrix with a programming code and create, as a principal application, a digital equalizer and use two additional buttons for other modes.[ES] Se trata de la automatizaciĂłn de un cubo de leds en todas sus aristas y diagonales, controlado mediante PLCAlbujer Rodriguez, N. (2015). Programming of a led matrix with a digital vu meter application. http://hdl.handle.net/10251/54532.TFG
Advanced automatic mixing tools for music
PhDThis thesis presents research on several independent systems that when
combined together can generate an automatic sound mix out of an unknown set
of multiâchannel inputs. The research explores the possibility of reproducing
the mixing decisions of a skilled audio engineer with minimal or no human
interaction. The research is restricted to nonâtime varying mixes for large room
acoustics. This research has applications in dynamic sound music concerts,
remote mixing, recording and postproduction as well as live mixing for
interactive scenes.
Currently, automated mixers are capable of saving a set of static mix
scenes that can be loaded for later use, but they lack the ability to adapt to a
different room or to a different set of inputs. In other words, they lack the
ability to automatically make mixing decisions. The automatic mixer research
depicted here distinguishes between the engineering mixing and the subjective
mixing contributions. This research aims to automate the technical tasks related
to audio mixing while freeing the audio engineer to perform the fineâtuning
involved in generating an aestheticallyâpleasing sound mix. Although the
system mainly deals with the technical constraints involved in generating an
audio mix, the developed system takes advantage of common practices
performed by sound engineers whenever possible. The system also makes use
of interâdependent channel information for controlling signal processing tasks
while aiming to maintain system stability at all times. A working
implementation of the system is described and subjective evaluation between a
human mix and the automatic mix is used to measure the success of the
automatic mixing tools
Development of a Software-Defined Underwater Acoustic Communication System
This report started with a brief history and recent development of underwater acoustic communication systems as well as software-defined radio technologies. Then, some challenges from underwater acoustic channels and available underwater acoustic communication modems are discussed. After finished introducing the basics of SDR and GNU Radio, a detailed description of implementing a software-defined acoustic communication system in GNU Radio are presented, along with some key concepts of the system.
Then, some hardware specifications are presented, following by detailed documentation on a software-defined acoustic communication system experiment with a host computer, a USRP, an acoustic hydrophone, and a hydrophone. At the end of Section 4, the results of the experiment are discussed.
Lastly, the conclusions of this report are made. Some possible directions for future work are suggested in Section 6
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