Design of low-voltage power efficient frequency dividers in folded MOS current mode logic

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology

An Ultra-Low-Power Front-End Neural Interface with Automatic Gain for Uncalibrated Monitoring

Accepted versio

A Flexible, Highly Integrated, Low Power pH Readout

Medical devices are widely employed in everyday life as wearable and implantable technologies make more and more technological breakthroughs. Implantable biosensors can be implanted into the human body for monitoring of relevant physiological parameters, such as pH value, glucose, lactate, CO2 [carbon dioxide], etc. For these applications the implantable unit needs a whole functional set of blocks such as micro- or nano-sensors, sensor signal processing and data generation units, wireless data transmitters etc., which require a well-designed implantable unit.Microelectronics technology with biosensors has caused more and more interest from both academic and industrial areas. With the advancement of microelectronics and microfabrication, it makes possible to fabricate a complete solution on an integrated chip with miniaturized size and low power consumption.This work presents a monolithic pH measurement system with power conditioning system for supply power derived from harvested energy. The proposed system includes a low-power, high linearity pH readout circuits with wide pH values (0-14) and a power conditioning unit based on low drop-out (LDO) voltage regulator. The readout circuit provides square-wave output with frequency being highly linear corresponding to the input pH values. To overcome the process variations, a simple calibration method is employed in the design which makes the output frequency stay constant over process, supply voltage and temperature variations. The prototype circuit is designed and fabricated in a standard 0.13-μm [micro-meter] CMOS process and shows good linearity to cover the entire pH value range from 0-14 while the voltage regulator provides a stable supply voltage for the system

Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance

A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays

The Integration of nearthreshold and subthreshold CMOS logic for energy minimization

With the rapid growth in the use of portable electronic devices, more emphasis has recently been placed on low-energy circuit design. Digital subthreshold complementary metal-oxide-semiconductor (CMOS) circuit design is one area of study that offers significant energy reduction by operating at a supply voltage substantially lower than the threshold voltage of the transistor. However, these energy savings come at a critical cost to performance, restricting its use to severely energy-constrained applications such as microsensor nodes. In an effort to mitigate this performance degradation in low-energy designs, nearthreshold circuit design has been proposed and implemented in digital circuits such as Intel\u27s energy-efficient hardware accelerator. The application spectrum of nearthreshold and subthreshold design could be broadened by integrating these cells into high-performance designs. This research focuses on the integration of characterized nearthreshold and subthreshold standard cells into high-performance functional modules. Within these functional modules, energy minimization is achieved while satisfying performance constraints by replacing non-critical path logic with nearthreshold and subthreshold logic cells. Specifically, the critical path method is used to bind the timing and energy constraints of the design. The design methodology was verified and tested with several benchmark circuits, including a cryptographic hash function, Skein. An average energy savings of 41.15% was observed at a circuit performance degradation factor of 10. The energy overhead of the level shifters accounted for at least 8.5% of the energy consumption of the optimized circuit, with an average energy overhead of 26.76%. A heuristic approach is developed for estimating the energy savings of the optimized design

Digital and analog TFET circuits: Design and benchmark

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions

Design of a Class-D Audio Amplifier With Analog Volume Control for Mobile Applications

A class-D audio amplifier with analog volume control (AVC) section and driver section for wireless and portable applications is proposed in this paper. The analog volume control section, including an integrator, an analog MUX, and a programmable gain amplifier (PGA) is implemented with three analog inputs (Audio, Voice, FM). For driver section, including a ramp generator, a comparator, a level shifter and a gate driver is designed to obtain a low distortion and a highefficiency. Designed with 0.18 um 1P6M CMOS technology, the class-D audio amplifier with analog volume control achieves a total root-mean-square (RMS) output power of 0.5W, a total harmonic distortion plus noise (THD+N) at the 8-Ω load less than 0.06%, and a power efficiency of 89.9% with a total area of 1.74mm2

Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs).We propose a mixed TFET\u2013MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET\u2013MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET\u2013MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions