Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.Comment: 5 pages, 2 figures, accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS) 202

Overcoming I/O bottleneck in superconducting quantum computing: multiplexed qubit control with ultra-low-power, base-temperature cryo-CMOS multiplexer

Large-scale superconducting quantum computing systems entail high-fidelity control and readout of large numbers of qubits at millikelvin temperatures, resulting in a massive input-output bottleneck. Cryo-electronics, based on complementary metal-oxide-semiconductor (CMOS) technology, may offer a scalable and versatile solution to overcome this bottleneck. However, detrimental effects due to cross-coupling between the electronic and thermal noise generated during cryo-electronics operation and the qubits need to be avoided. Here we present an ultra-low power radio-frequency (RF) multiplexing cryo-electronics solution operating below 15 mK that allows for control and interfacing of superconducting qubits with minimal cross-coupling. We benchmark its performance by interfacing it with a superconducting qubit and observe that the qubit's relaxation times ($T_1$) are unaffected, while the coherence times ($T_2$) are only minimally affected in both static and dynamic operation. Using the multiplexer, single qubit gate fidelities above 99.9%, i.e., well above the threshold for surface-code based quantum error-correction, can be achieved with appropriate thermal filtering. In addition, we demonstrate the capability of time-division-multiplexed qubit control by dynamically windowing calibrated qubit control pulses. Our results show that cryo-CMOS multiplexers could be used to significantly reduce the wiring resources for large-scale qubit device characterization, large-scale quantum processor control and quantum error correction protocols.Comment: 16+6 pages, 4+1+5 figures, 1 tabl

CMOS Quantum Computing: Toward A Quantum Computer System-on-Chip

Quantum computing is experiencing the transition from a scientific to an engineering field with the promise to revolutionize an extensive range of applications demanding high-performance computing. Many implementation approaches have been pursued for quantum computing systems, where currently the main streams can be identified based on superconducting, photonic, trapped-ion, and semiconductor qubits. Semiconductor-based quantum computing, specifically using CMOS technologies, is promising as it provides potential for the integration of qubits with their control and readout circuits on a single chip. This paves the way for the realization of a large-scale quantum computing system for solving practical problems. In this paper, we present an overview and future perspective of CMOS quantum computing, exploring developed semiconductor qubit structures, quantum gates, as well as control and readout circuits, with a focus on the promises and challenges of CMOS implementation