Combined Crosstalk Avoidance Code with Error Control Code for Detection and Correction of Random and Burst Errors

Error correction codes are majorly important to detect and correct occurred errors because of various noise sources. When the technology is scaling down, the effect of noise sources is high. The coupling capacitance is one of the main constraints to affect the performance of on-chip interconnects. Because of coupling capacitance, the crosstalk is introduced at on-chip interconnecting wires. To control the single or multiple errors, an efficient error correction code is required. By combining crosstalk avoidance with error control code, the reliable intercommunication is obtained in network-on-chip (NoC)-based system on chip (SoC). To reduce the power consumption of error control codes, the bus invert-based low-power code is integrated to network interface of NoC. The advanced work is designed and implemented with Xilinx 14.7; thereby the performance of improved NoC is evaluated and compared with existing work. The 8×8 mesh-based NoC is simulated at various traffic patterns to analyze the energy dissipation and average data packet latency

Comparative Reliability Analysis between Horizontal-Vertical-Diagonal Code and Code with Crosstalk Avoidance and Error Correction for NoC Interconnects

Ensuring reliable data transmission in Network on Chip (NoC) is one of the most challenging tasks, especially in noisy environments. As crosstalk, interference, and radiation were increased with manufacturers' increasing tendency to reduce the area, increase the frequencies, and reduce the voltages.  So many Error Control Codes (ECC) were proposed with different error detection and correction capacities and various degrees of complexity. Code with Crosstalk Avoidance and Error Correction (CCAEC) for network-on-chip interconnects uses simple parity check bits as the main technique to get high error correction capacity. Per this work, this coding scheme corrects up to 12 random errors, representing a high correction capacity compared with many other code schemes. This candidate has high correction capability but with a high codeword size. In this work, the CCAEC code is compared to another well-known code scheme called Horizontal-Vertical-Diagonal (HVD) error detecting and correcting code through reliability analysis by deriving a new accurate mathematical model for the probability of residual error Pres for both code schemes and confirming it by simulation results for both schemes. The results showed that the HVD code could correct all single, double, and triple errors and failed to correct only 3.3 % of states of quadric errors. In comparison, the CCAEC code can correct a single error and fails in 1.5%, 7.2%, and 16.4% cases of double, triple, and quadric errors, respectively. As a result, the HVD has better reliability than CCAEC and has lower overhead; making it a promising coding scheme to handle the reliability issues for NoC

Reliability-aware multi-segmented bus architecture for photonic networks-on-chip

Network-on-chip (NoC) has emerged as an enabling platform for connecting hundreds of cores on a single chip, allowing for a structured, scalable system when compared to traditional on-chip buses. However, the multi-hop wireline paths in traditional NoCs result in high latency and energy dissipation causing an overall degradation in performance, especially for increasing system size. To alleviate this problem a few radically different interconnect technologies are envisioned. One such method of interconnecting different cores in NoCs is photonic interconnects. Photonic NoCs are on-chip communications networks in which information is transmitted in the form of optical signals. Photonic interconnection is one of the leading examples of emerging technology for on-chip interconnects. Existing innovative photonic NoC architectures have improved performance and reduced energy dissipation. Most architectures use Wavelength Division Multiplexing (WDM) on the photonic waveguides to increase the data bandwidth. However they have issues relating to reliability, such as waveguide losses and adjacent channel crosstalk. These phenomena could have a crippling effect on a system, and most current architectures do not address these effects. A newly proposed topology, known as the Multiple-Segmented Bus topology, or MSB, has shown promise for solving, or at least reducing, many of the problems plaguing the design of photonic networks using a modification of a folded torus to transmit different wavelength signals simultaneously. The MSB segments the waveguides into smaller parts to limit the waveguide losses. The formal performance evaluation of this proposed architecture has not been completed. This thesis will analyze the performance of such a network when implemented as a NoC in terms of data bandwidth, energy dissipation, latency, and reliability. By analyzing and comparing performance, energy dissipations, and reliability, the MSB-based photonic NoC (MSB-PNoC) can be compared to other state-of-the-art photonic NoCs to determine the feasibility of this topology for future network-on-chip designs

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects

Siirretty Doriast

Communication Reliability in Network on Chip Designs

The performance of low latency Network on Chip (NoC) architectures, which incorporate fast bypass paths to reduce communication latency, is limited by crosstalk induced skewing of signal transitions on link wires. As a result of crosstalk interactions between wires, signal transitions belonging to the same flit or bit vector arrive at the destination at different times and are likely to violate setup and hold time constraints for the design. This thesis proposes a two-step technique: TransSync- RecSync, to dynamically eliminate packet errors resulting from inter-bit-line transition skew. The proposed approach adds minimally to router complexity and involves no wire overhead. The actual throughput of NoC designs with asynchronous bypass designs is evaluated and the benefits of augmenting such schemes with the proposed design are studied. The TransSync, TransSync-2-lines and RecSync schemes described here are found to improve the average communication latency by 26%, 20% and 38% respectively in a 7X7 mesh NoC with asynchronous bypass channel. This work also evaluates the bit-error ratio (BER) performance of several existing crosstalk avoidance and error correcting schemes and compares them to that of the proposed schemes. Both TransSync and RecSync scheme are dynamic in nature and can be switched on and off on-the-fly. The proposed schemes can therefore be employed to impart unequal error protection (UEP) against intra-flit skewing on NoC links. In the UEP, a larger fraction of the energy budget is spent in providing protection to those parts of the data being transmitted on the link which have a higher priority, while expending smaller effort in protecting relatively less important parts of the data. This allows us to achieve the prescribed level of performance with lower levels of power. The benefits of the presented technique are illustrated using an H.264 video decoder system-on-chip (SoC) employing NoC architecture. We show that for Akyio test streams transmitted over 3mm long link wires, the power consumption can be reduced by as much as 20% at the cost of an acceptable degradation in average peak signal to noise ratio (PSNR) with UEP

Interference analysis for optical wireless communications in Network-on-Chip (NoC) scenarios

Optical wireless (OW) communications, besides being of great interest for indoor and outdoor applications, have been recently proposed as a powerful alternative to the existing wired and wireless radio frequency (RF) interconnects in network-on-chips (NoCs). Design and analysis of networks with OW links require a careful investigation of cross-link interference, which impacts considerably the efficiency of systems that reuse the same channel for multiple transmissions. Yet, there is no comprehensive analysis of interference for OW NoCs, and the analyses of crosstalk in optical waveguide communications usually rely on synchronous data transmissions. A novel framework for the analysis of on-chip OW communications in the presence of cross-link cochannel interference and noise is proposed, where asynchronous data transmissions are considered. Self-beating of interfering signals is also considered, which was often neglected in previous literature. The bit error probability (BEP) for arbitrary number of interfering sources is derived as a function of signal-to-noise ratio (SNR), interference powers, detection threshold and pulse shaping, using both exact and approximation methods. The proposed analysis can be applied to both noise- and interference-limited cases, and enables a system designer to evaluate reuse distance between links that share the same optical carrier for simultaneous communication in NoCs

Global Congestion and Fault Aware Wireless Interconnection Framework for Multicore Systems

Multicore processors are getting more common in the implementation of all type of computing demands, starting from personal computers to the large server farms for high computational demanding applications. The network-on-chip provides a better alternative to the traditional bus based communication infrastructure for this multicore system. Conventional wire-based NoC interconnect faces constraints due to their long multi-hop latency and high power consumption. Furthermore high traffic generating applications sometimes creates congestion in such system further degrading the systems performance. In this thesis work, a novel two-state congestion aware wireless interconnection framework for network chip is presented. This WiNoC system was designed to able to dynamically redirect traffic to avoid congestion based on network condition information shared among all the core tiles in the system. Hence a novel routing scheme and a two-state MAC protocol is proposed based on a proposed two layer hybrid mesh-based NoC architecture. The underlying mesh network is connected via wired-based interconnect and on top of that a shared wireless interconnect framework is added for single-hop communication. The routing scheme is non-deterministic in nature and utilizes the principles from existing dynamic routing algorithms. The MAC protocol for the wireless interface works in two modes. The first is data mode where a token-based protocol is utilized to transfer core data. And the second mode is the control mode where a broadcast-based communication protocol is used to share the network congestion information. The work details the switching methodology between these two modes and also explain, how the routing scheme utilizes the congestion information (gathered during the control mode) to route data packets during normal operation mode. The proposed work was modeled in a cycle accurate network simulator and its performance were evaluated against traditional NoC and WiNoC designs

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levelsSiirretty Doriast