Improving timing verification and delay testing methodologies for IC designs

textThe task of ensuring the correct temporal behavior of IC designs, both before and after fabrication, is extremely important. It is becoming even more imperative as the demand for performance increases and process technology advances into the deep sub-micron region. This dissertation tackles the key issues in the timing verification and delay testing methodologies. An efficient methodology is presented to identify false timing paths in the timing verification methodology which utilizes ATPG technique and timing information from an ordered list of timing paths according to the delay information. This dissertation also presents a speed binning methodology which utilizes structural delay tests successfully instead of functional tests. In addition, it establishes a methodology which quantifies the correlation between the timing verification prediction and actual silicon measurement of timing paths. This quantification methodology lays the foundation for further research to study the impact of deep submicron effects on design performanceElectrical and Computer Engineerin

Choose-Your-Own Adventure: A Lightweight, High-Performance Approach To Defect And Variation Mitigation In Reconfigurable Logic

For field-programmable gate arrays (FPGAs), fine-grained pre-computed alternative configurations, combined with simple test-based selection, produce limited per-chip specialization to counter yield loss, increased delay, and increased energy costs that come from fabrication defects and variation. This lightweight approach achieves much of the benefit of knowledge-based full specialization while reducing to practical, palatable levels the computational, testing, and load-time costs that obstruct the application of the knowledge-based approach. In practice this may more than double the power-limited computational capabilities of dies fabricated with 22nm technologies. Contributions of this work: • Choose-Your-own-Adventure (CYA), a novel, lightweight, scalable methodology to achieve defect and variation mitigation • Implementation of CYA, including preparatory components (generation of diverse alternative paths) and FPGA load-time components • Detailed performance characterization of CYA – Comparison to conventional loading and dynamic frequency and voltage scaling (DFVS) – Limit studies to characterize the quality of the CYA implementation and identify potential areas for further optimizatio

Investigation of a piezo-polymer array transducer for pulse-echo ultrasonic material examinations

The aim of this investigation was to make a flexible array of pulse-echo ultrasound transducers by etching two orthogonal linear arrays of conducting elements into the metallisation of either side of a sheet of PVdF. These would then be multiplexed under computer control in an X-Y raster, thereby forming an image of subsurface defects in a material specimen. A potential source model was used to predict the sensitivity of a single element air-backed transducer far from resonance. Initial investigations confirmed the predictions, and reaffirmed the results of previous workers. In making a prototype array, it was found necessary to use a bi-laminar arrangement with a central ground plane, due to difficulties with crosstalk and charge leakage into the specimen materials. The radiation pattern of this array was tested and found to agree with the predictions for Fraunhofer (Far-Field) radiation. A 10 MHz analogue to digital converter was constructed to interface with the IBM-PC clone as a transient recorder, through a data capture program written in 'C'. However, the electrical noise generated by the PC was found to interfere strongly with the signal from the array transducer. A wide-band amplifier and full-wave rectifier was then added to the multiplexer and A/D converter, and the system enclosed in an electrically isolated environment, which made it possible to obtain clear signal data from the transducer. Non-linear regression was implemented in the software, to smooth the data and locate echo peaks, and the most frequently occurring peak separation was used to indicate sample thickness at that location in a false-colour mapping on the screen of the PC