A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

Electronics and data acquisition demonstrator for a kinetic inductance camera

A prototype of digital frequency multiplexing electronics allowing the real time monitoring of kinetic inductance detector (KIDs) arrays for mm-wave astronomy has been developed. It requires only 2 coaxial cables for instrumenting a large array. For that, an excitation comb of frequencies is generated and fed through the detector. The direct frequency synthesis and the data acquisition relies heavily on a large FPGA using parallelized and pipelined processing. The prototype can instrument 128 resonators (pixels) over a bandwidth of 125 MHz. This paper describes the technical solution chosen, the algorithm used and the results obtained

Development of the photomultiplier tube readout system for the first Large-Sized Telescope of the Cherenkov Telescope Array

The Cherenkov Telescope Array (CTA) is the next generation ground-based very high energy gamma-ray observatory. The Large-Sized Telescope (LST) of CTA targets 20 GeV -- 1 TeV gamma rays and has 1855 photomultiplier tubes (PMTs) installed in the focal plane camera. With the 23 m mirror dish, the night sky background (NSB) rate amounts to several hundreds MHz per pixel. In order to record clean images of gamma-ray showers with minimal NSB contamination, a fast sampling of the signal waveform is required so that the signal integration time can be as short as the Cherenkov light flash duration (a few ns). We have developed a readout board which samples waveforms of seven PMTs per board at a GHz rate. Since a GHz FADC has a high power consumption, leading to large heat dissipation, we adopted the analog memory ASIC "DRS4". The sampler has 1024 capacitors per channel and can sample the waveform at a GHz rate. Four channels of a chip are cascaded to obtain deeper sampling depth with 4096 capacitors. After a trigger is generated in a mezzanine on the board, the waveform stored in the capacitor array is subsequently digitized with a low speed (33 MHz) ADC and transferred via the FPGA-based Gigabit Ethernet to a data acquisition system. Both a low power consumption (2.64 W per channel) and high speed sampling with a bandwidth of $>$300 MHz have been achieved. In addition, in order to increase the dynamic range of the readout we adopted a two gain system achieving from 0.2 up to 2000 photoelectrons in total. We finalized the board design for the first LST and proceeded to mass production. Performance of produced boards are being checked with a series of quality control (QC) tests. We report the readout board specifications and QC results.Comment: In Proceedings of the 34th International Cosmic Ray Conference (ICRC2015), The Hague, The Netherlands. All CTA contributions at arXiv:1508.0589

HgCdTe 256x256 NWIR FPA

Researchers developed a HgCdTe 256x256 focal plane array (FPA) which operates in the 1 to 5 micron band. This is presently the largest demonstrated HgCdTe FPA. The detector material is HgCdTe on sapphire (PACE-1 technology) which has a low thermal expansion mismatch with silicon. The multiplexer is a CMOS FET-switch device processed through a commercial silicon foundry. The multiplexer input is direct injection and the charge capacity is about 2 times 10 to the 7th power electrons. The kTC limited read noise is 400 electrons. Researchers demonstrated high background imaging using the device. The broadband quantum efficiency is measured to be 59 percent. Dark currents less than 0.1 pA were measured at 77 K for detectors processed on PACE-1 material with 4.9 microns cutoff. The dark currents decrease as the temperature is lowered, and researchers are presently studying the T less than 77 K characteristics. The interconnect yield is greater than 95 percent. The devices are available for astronomical applications

Receiver architecture of the thousand-element array (THEA)

As part of the development of a new international radio-telescope SKA (Square Kilometre Array), an outdoor phasedarray prototype, the THousand Element Array (THEA), is being developed at NFRA. THEA is a phased array with 1024 active elements distributed on a regular grid over a surface of approximately 16 m2. The array is organised into 16 units denoted as tiles. THEA operates in the frequency band from 750 to 1500 MHz.\ud On a tile the signals from 64 antenna elements are converted into two independent RF beams. Two times 16 beams can be made simultaneously with full sensitivity by the real-time digital beam former of the THEA system. At the output of each tile the analog RF signal from a beam is converted into a 2 × 12-bit digital quadrature representation by a receiver system.\ud A double super-heterodyne architecture is used to mix the signal band of interest to an intermediate frequency of 210 MHz. The IF-signal is shifted to baseband by means of a partly digitally implemented I/Q mixer scheme. After a quadrature mixer stage, the I and Q signals are digitised by means of 12 bit A/D converters at 40 MS/s. Implementing a part of the mixing scheme digitally offers the flexibility to use different I/Q architectures, e.g. Hartley and Weaver mixer setups. This way the effect of RFI in different mixing architectures can be analyzed. After the digital processing, the samples are multiplexed, serialised and transported over fibres to the central adaptive digital beam former unit where the signals from all tiles are combined giving 32 beams.\ud This paper focuses on the design choices and the final implementation of the THEA system. In particular, the receiver architecture is addressed. A digital solution is presented, which enables switching between a Hartley and a Weaver based mixer scheme

Boolean Satisfiability in Electronic Design Automation

Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other fields of Computer Science and Engineering. In recent years, new and efficient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT “packages” are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem. Specifically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used for solving SAT, including those that have seen widespread use in specific EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks