2,541 research outputs found

    Low-Power, High-Speed Transceivers for Network-on-Chip Communication

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    Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

    Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.

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    A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design

    High–Speed Data Transmission Subsystem of the SEOSAR/PAZ Satellite

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    This paper analyzes a digital interface and bus system modeling and optimization of the SEOSAR/PAZ Earth Observation satellite. The important part of the satellite is an X–band Synthetic Aperture Radar instrument that integrates 384 Transmit/Receive Modules located in 12 antenna panels 7.5 m away from the central processor and controlled by a synchronous 10 Mbps bidirectional serial protocol. This type of mid–range point–to–multipoint transmission is affected by bit errors due to crosstalk, transmission line attenuation and impedance mismatches. The high–speed data communication network has been designed to optimize the transmission by using a simulation model of the data distribution system which takes into account the worst–case scenario and by developing a lab–scaled prototype which exhibits BER of 10-11 for an interfering signal of 10 Vpp. The result is a point–to–multipoint bidirectional transmission network optimized in both directions with optimal values of loads and equalization resistors. This high–speed data transmission subsystem provides a compact design through a simple solution

    Compact and accurate models of large single-wall carbon-nanotube interconnects

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    Single-wall carbon nanotubes (SWCNTs) have been proposed for very large scale integration interconnect applications and their modeling is carried out using the multiconductor transmission line (MTL) formulation. Their time-domain analysis has some simulation issues related to the high number of SWCNTs within each bundle, which results in a highly complex model and loss of accuracy in the case of long interconnects. In recent years, several techniques have been proposed to reduce the complexity of the model whose accuracy decreases as the interconnection length increases. This paper presents a rigorous new technique to generate accurate reduced-order models of large SWCNT interconnects. The frequency response of the MTL is computed by using the spectral form of the dyadic Green's function of the 1-D propagation problem and the model complexity is reduced using rational-model identification techniques. The proposed approach is validated by numerical results involving hundreds of SWCNTs, which confirm its capability of reducing the complexity of the model, while preserving accuracy over a wide frequency range

    On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

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    This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted
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