Doctor of Philosophy

dissertationRecent breakthroughs in silicon photonics technology are enabling the integration of optical devices into silicon-based semiconductor processes. Photonics technology enables high-speed, high-bandwidth, and high-fidelity communications on the chip-scale-an important development in an increasingly communications-oriented semiconductor world. Significant developments in silicon photonic manufacturing and integration are also enabling investigations into applications beyond that of traditional telecom: sensing, filtering, signal processing, quantum technology-and even optical computing. In effect, we are now seeing a convergence of communications and computation, where the traditional roles of optics and microelectronics are becoming blurred. As the applications for opto-electronic integrated circuits (OEICs) are developed, and manufacturing capabilities expand, design support is necessary to fully exploit the potential of this optics technology. Such design support for moving beyond custom-design to automated synthesis and optimization is not well developed. Scalability requires abstractions, which in turn enables and requires the use of optimization algorithms and design methodology flows. Design automation represents an opportunity to take OEIC design to a larger scale, facilitating design-space exploration, and laying the foundation for current and future optical applications-thus fully realizing the potential of this technology. This dissertation proposes design automation for integrated optic system design. Using a buildingblock model for optical devices, we provide an EDA-inspired design flow and methodologies for optical design automation. Underlying these flows and methodologies are new supporting techniques in behavioral and physical synthesis, as well as device-resynthesis techniques for thermal-aware system integration. We also provide modeling for optical devices and determine optimization and constraint parameters that guide the automation techniques. Our techniques and methodologies are then applied to the design and optimization of optical circuits and devices. Experimental results are analyzed to evaluate their efficacy. We conclude with discussions on the contributions and limitations of the approaches in the context of optical design automation, and describe the tremendous opportunities for future research in design automation for integrated optics

Crossing-aware channel routing for photonic waveguides

pre-printAbstract-Silicon photonics technology is progressing at a rapid pace. Despite greatly expanded manufacturing capability, physical design of integrated optical circuits currently lacks the level of automation found in VLSI design. A key component of integrated optic design is waveguide routing; however, unlike VLSI, where signal nets are routed with metal layers and vias, photonic waveguides are fabricated in planar substrates. For many applications, our studies show that the waveguide routing problem can be formulated as planar channel routing. Signal losses become a major factor due to the insertion losses of planar waveguide crossings. Channel routing must therefore take into account these losses. This paper investigates methods for adapting traditional VLSI channel routing techniques for integrated optics - specifically, a technique based on left-edge-style track assignment. We show how incorporating waveguide crossing constraints into the underlying constraint model affects the routing solution, and describe the necessary modifications and extensions to the routing technique to properly exploit optical technology. We implement the channel router, describe the experimental results, and compare the cost of solutions with respect to waveguide crossings, corresponding to signal loss, and channel height

Channel routing for integrated optics

pre-printIncreasing scope and applications of integrated optics necessitates the development of automated techniques for physical design of optical systems. This paper presents an automated, planar channel routing technique for integrated optical waveguides. Integrated optics is a planar technology and lacks the inherent signal restoration capabilities of static-CMOS. Therefore, signal loss minimization-as a function of waveguide crossings and bends-is the primary objective of this technique. This is in contrast to track and wire-length minimization of traditional VLSI routing. Our optical channel router guarantees minimal waveguide crossings by drawing upon sorting-based techniques for waveguide routing. To further improve our solutions in terms of signal loss, we extend the router to reduce the number of bends produced during routing. Finally, we implement the optical channel routing technique and describe the experimental results, comparing the costs of routing solutions with respect to waveguide crossings, bends, and channel height

Crosstalk Noise Aware System For WDM-Based Optical Network on Chip

Network on chip (NoC) is presented as a promising solution to face off the growing up of the data exchange in the multiprocessor system-on-chip (MPSoC). However, the traditional NoC faces two main problems: the bandwidth and the energy consumption. To face off these problems, a new technology in MPSoC, namely, optical network-on-chip (ONoC) has been introduced which it uses the optical communication to guaranty a high performance in communication between cores. In addition, wavelength division multiplexing (WDM) is exploited in ONoC to reach a high rate of bandwidth. Nevertheless, the transparency nature of the ONoC components induce crosstalk noise to the optical signals, which it has a direct effect to the signal-to-noise ratio (SNR) then decrease the performance of the ONoC. In this paper, we proposed a new system to control these impairments in the network in order to detect and monitor crosstalk noise in WDM-based ONoC. Furthermore, the crosstalk monitoring system is a distributed hardware system designed and test with the different optical components according the various network topology used in ONoC. The register-transfer level (RTL) hardware design and implementation of this system can result in high reliability, scalability and efficiency with running time less than 20 ms

Photonics design tool for advanced CMOS nodes

Recently, the authors have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigour that is embodied in the 10 000 to 50 000 design rules that these designs must comply within advanced complementary metal-oxide semiconductor manufacturing. Here, the authors present a photonic design automation tool which allows automatic generation of layouts without design-rule violations. This tool is written in SKILL, the native language of the mainstream electric design automation software, Cadence. This allows seamless integration of photonic and electronic design in a single environment. The tool leverages intuitive photonic layer definitions, allowing the designer to focus on the physical properties rather than on technology-dependent details. For the first time the authors present an algorithm for removal of design-rule violations from photonic layouts based on Manhattan discretisation, Boolean and sizing operations. This algorithm is not limited to the implementation in SKILL, and can in principle be implemented in any scripting language. Connectivity is achieved with software-defined waveguide ports and low-level procedures that enable auto-routing of waveguide connections.Comment: 5 pages, 10 figure

An Overview on Application of Machine Learning Techniques in Optical Networks

Today's telecommunication networks have become sources of enormous amounts of widely heterogeneous data. This information can be retrieved from network traffic traces, network alarms, signal quality indicators, users' behavioral data, etc. Advanced mathematical tools are required to extract meaningful information from these data and take decisions pertaining to the proper functioning of the networks from the network-generated data. Among these mathematical tools, Machine Learning (ML) is regarded as one of the most promising methodological approaches to perform network-data analysis and enable automated network self-configuration and fault management. The adoption of ML techniques in the field of optical communication networks is motivated by the unprecedented growth of network complexity faced by optical networks in the last few years. Such complexity increase is due to the introduction of a huge number of adjustable and interdependent system parameters (e.g., routing configurations, modulation format, symbol rate, coding schemes, etc.) that are enabled by the usage of coherent transmission/reception technologies, advanced digital signal processing and compensation of nonlinear effects in optical fiber propagation. In this paper we provide an overview of the application of ML to optical communications and networking. We classify and survey relevant literature dealing with the topic, and we also provide an introductory tutorial on ML for researchers and practitioners interested in this field. Although a good number of research papers have recently appeared, the application of ML to optical networks is still in its infancy: to stimulate further work in this area, we conclude the paper proposing new possible research directions

Architectural Exploration and Design Methodologies of Photonic Interconnection Networks

Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on- and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this work, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment called PhoenixSim. Next, we leverage PhoenixSim for the study of chip-scale photonic networks. We examine several photonic networks through the synergistic study of both physical-layer metrics and system-level metrics. This holistic analysis method enables us to provide deeper insight into architecture scalability since it considers insertion loss, crosstalk, and power dissipation. In addition to these novel physical-layer metrics, traditional system-level metrics of bandwidth and latency are also obtained. Lastly, we propose a novel routing architecture known as wavelength-selective spatial routing. This routing architecture is analogous to electronic virtual channels since it enables the transmission of multiple logical optical channels through a single physical plane (i.e. the waveguides). The available wavelength channels are partitioned into separate groups, and each group is routed independently in the network. Each partition is spectrally multiplexed, as opposed to temporally multiplexed in the electronic case. The wavelength-selective spatial routing technique benefits network designers by provider lower contention and increased path diversity

Master of Science

thesisAdvances in silicon photonics are enabling hybrid integration of optoelectronic circuits alongside current complementary metal-oxide-semiconductor (CMOS) technologies. To fully exploit the capability of this integration, it is important to explore the effects of thermal gradients on optoelectronic devices. The sensitivity of optical components to temperature variation gives rise to design issues in silicon on insulator (SOI) optoelectronic technology. The thermo-electric effect becomes problematic with the integration of hybrid optoelectronic systems, where heat is generated from electrical components. Through the thermo-optic effect, the optical signals are in turn affected and compensation is necessary. To improve the capability of optical SOI designs, optical-wave-simulation models and the characteristic thermal operating environment need to be integrated to ensure proper operation. In order to exploit the potential for compensation by virtue of resynthesis, temperature characterization on a system level is required. Thermal characterization within the flow of physical design automation tools for hybrid optoelectronic technology enables device resynthesis and validation at a system level. Additionally, thermally-aware routing and placement would be possible. A simplified abstraction will help in the active design process, within the contemporary computer-aided design (CAD) flow when designing optoelectronic features. This thesis investigates an abstraction model to characterize the effect of a temperature gradient on optoelectronic circuit operation. To make the approach scalable, reduced order computations are desired that effectively model the effect of temperature on an optoelectronic layout; this is achieved using an electrical analogy to heat flow. Given an optoelectronic circuit, using a thermal resistance network to abstract thermal flow, we compute the temperature distribution throughout the layout. Subsequently, we show how this thermal distribution across the optoelectronic system layout can be integrated within optoelectronic device- and system-level analysis tools

Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer

This work presents a bottom-up abstraction procedure based on the design-flow FDTD + SystemC suitable for the modelling of optical Networks-on-Chip. In this procedure, a complex network is decomposed into elementary switching elements whose input-output behavior is described by means of scattering parameters models. The parameters of each elementary block are then determined through 2D-FDTD simulation, and the resulting analytical models are exported within functional blocks in SystemC environment. The inherent modularity and scalability of theS-matrix formalism are preserved inside SystemC, thus allowing the incremental composition and successive characterization of complex topologies typically out of reach for full-vectorial electromagnetic simulators. The consistency of the outlined approach is verified, in the first instance, by performing a SystemC analysis of a four-input, four-output ports switch and making a comparison with the results of 2D-FDTD simulations of the same device. Finally, a further complex network encompassing 160 microrings is investigated, the losses over each routing path are calculated, and the minimum amount of power needed to guarantee an assigned BER is determined. This work is a basic step in the direction of an automatic technology-aware network-level simulation framework capable of assembling complex optical switching fabrics, while at the same time assessing the practical feasibility and effectiveness at the physical/technological level