587 research outputs found

    Magnetic racetrack memory: from physics to the cusp of applications within a decade

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    Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the potential to overcome fundamental constraints of existing memory and storage devices. It is unique in that its core differentiating feature is the movement of data, which is composed of magnetic domain walls (DWs), by short current pulses. This enables more data to be stored per unit area compared to any other current technologies. On the one hand, RTM has the potential for mass data storage with unlimited endurance using considerably less energy than today's technologies. On the other hand, RTM promises an ultrafast nonvolatile memory competitive with static random access memory (SRAM) but with a much smaller footprint. During the last decade, the discovery of novel physical mechanisms to operate RTM has led to a major enhancement in the efficiency with which nanoscopic, chiral DWs can be manipulated. New materials and artificially atomically engineered thin-film structures have been found to increase the speed and lower the threshold current with which the data bits can be manipulated. With these recent developments, RTM has attracted the attention of the computer architecture community that has evaluated the use of RTM at various levels in the memory stack. Recent studies advocate RTM as a promising compromise between, on the one hand, power-hungry, volatile memories and, on the other hand, slow, nonvolatile storage. By optimizing the memory subsystem, significant performance improvements can be achieved, enabling a new era of cache, graphical processing units, and high capacity memory devices. In this article, we provide an overview of the major developments of RTM technology from both the physics and computer architecture perspectives over the past decade. We identify the remaining challenges and give an outlook on its future

    Coding for Racetrack Memories

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    Racetrack memory is a new technology which utilizes magnetic domains along a nanoscopic wire in order to obtain extremely high storage density. In racetrack memory, each magnetic domain can store a single bit of information, which can be sensed by a reading port (head). The memory has a tape-like structure which supports a shift operation that moves the domains to be read sequentially by the head. In order to increase the memory's speed, prior work studied how to minimize the latency of the shift operation, while the no less important reliability of this operation has received only a little attention. In this work we design codes which combat shift errors in racetrack memory, called position errors. Namely, shifting the domains is not an error-free operation and the domains may be over-shifted or are not shifted, which can be modeled as deletions and sticky insertions. While it is possible to use conventional deletion and insertion-correcting codes, we tackle this problem with the special structure of racetrack memory, where the domains can be read by multiple heads. Each head outputs a noisy version of the stored data and the multiple outputs are combined in order to reconstruct the data. Under this paradigm, we will show that it is possible to correct, with at most a single bit of redundancy, dd deletions with d+1d+1 heads if the heads are well-separated. Similar results are provided for burst of deletions, sticky insertions and combinations of both deletions and sticky insertions

    Perpendicular Reading of Single Confined Magnetic Skyrmions

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    Thin-film sub-5 nm magnetic skyrmions constitute an ultimate scaling alternative for future digital data storage. Skyrmions are robust non-collinear spin-textures that can be moved and manipulated by small electrical currents. We show here an innovative technique to detect isolated nanoskyrmions with a current-perpendicular-to-plane geometry, which has immediate implications for device concepts. We explore the physics behind such a mechanism by studying the atomistic electronic structure of the magnetic quasiparticles. We investigate how the isolated skyrmion local-density-of-states which tunnels into the vacuum, when compared to the ferromagnetic background, is modified by the site-dependent spin-mixing of electronic states with different relative canting angles. Local transport properties are sensitive to this effect, as we report an atomistic conductance anisotropy of over 20% for magnetic skyrmions in Pd/Fe/Ir(111) thin-films. In single skyrmions, engineering this spin-mixing magnetoresistance possibly could be incorporated in future magnetic storage technologies

    Design of an integrated hybrid plasmonic-photonic device for all-optical switching and reading of spintronic memory

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    We introduce a novel integrated hybrid plasmonic-photonic device for all-optical switching and reading of nanoscale ferrimagnet bits. The racetrack memory made of synthetic ferrimagnetic material with a perpendicular magnetic anisotropy is coupled on to a photonic waveguide onto the indium phosphide membrane on silicon platform. The device which is composed of a double V-shaped gold plasmonic nanoantenna coupled with a photonic crystal cavity can enable switching and reading of the magnetization state in nanoscale magnetic bits by enhancing the absorbed energy density and polar magneto-optical Kerr effect (PMOKE) locally beyond the diffraction limit. Using a three-dimensional finite-difference time-domain method, we numerically show that our device can switch and read the magnetization state in targeted bits down to ~100 nm in the presence of oppositely magnetized background regions in the racetrack with widths of 30 to 120 nm, clearly outperforming a bare photonic waveguide. Our hybrid device tackles the challenges of nonlinear absorption in the waveguide, weak PMOKE, and size mismatch between spintronics and integrated photonics. Thus, it provides missing link between the integrated photonics and nanoscale spintronics, expediting the development of ultrafast and energy efficient advanced on-chip applications

    Design and Code Optimization for Systems with Next-generation Racetrack Memories

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    With the rise of computationally expensive application domains such as machine learning, genomics, and fluids simulation, the quest for performance and energy-efficient computing has gained unprecedented momentum. The significant increase in computing and memory devices in modern systems has resulted in an unsustainable surge in energy consumption, a substantial portion of which is attributed to the memory system. The scaling of conventional memory technologies and their suitability for the next-generation system is also questionable. This has led to the emergence and rise of nonvolatile memory ( NVM ) technologies. Today, in different development stages, several NVM technologies are competing for their rapid access to the market. Racetrack memory ( RTM ) is one such nonvolatile memory technology that promises SRAM -comparable latency, reduced energy consumption, and unprecedented density compared to other technologies. However, racetrack memory ( RTM ) is sequential in nature, i.e., data in an RTM cell needs to be shifted to an access port before it can be accessed. These shift operations incur performance and energy penalties. An ideal RTM , requiring at most one shift per access, can easily outperform SRAM . However, in the worst-cast shifting scenario, RTM can be an order of magnitude slower than SRAM . This thesis presents an overview of the RTM device physics, its evolution, strengths and challenges, and its application in the memory subsystem. We develop tools that allow the programmability and modeling of RTM -based systems. For shifts minimization, we propose a set of techniques including optimal, near-optimal, and evolutionary algorithms for efficient scalar and instruction placement in RTMs . For array accesses, we explore schedule and layout transformations that eliminate the longer overhead shifts in RTMs . We present an automatic compilation framework that analyzes static control flow programs and transforms the loop traversal order and memory layout to maximize accesses to consecutive RTM locations and minimize shifts. We develop a simulation framework called RTSim that models various RTM parameters and enables accurate architectural level simulation. Finally, to demonstrate the RTM potential in non-Von-Neumann in-memory computing paradigms, we exploit its device attributes to implement logic and arithmetic operations. As a concrete use-case, we implement an entire hyperdimensional computing framework in RTM to accelerate the language recognition problem. Our evaluation shows considerable performance and energy improvements compared to conventional Von-Neumann models and state-of-the-art accelerators

    Shiftsreduce: Minimizing shifts in racetrack memory 4.0

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    Racetrack memories (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. This article presents data-placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime, thereby minimizing the number of shifts. We present an integer linear programming (ILP) formulation for optimal data placement in RMs, and we revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5%, outperforming the state of the art by up to 16.1%

    Overview of emerging nonvolatile memory technologies

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