Gestión de jerarquías de memoria híbridas a nivel de sistema

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadoras y Automática y de Ku Leuven, Arenberg Doctoral School, Faculty of Engineering Science, leída el 11/05/2017.In electronics and computer science, the term ‘memory’ generally refers to devices that are used to store information that we use in various appliances ranging from our PCs to all hand-held devices, smart appliances etc. Primary/main memory is used for storage systems that function at a high speed (i.e. RAM). The primary memory is often associated with addressable semiconductor memory, i.e. integrated circuits consisting of silicon-based transistors, used for example as primary memory but also other purposes in computers and other digital electronic devices. The secondary/auxiliary memory, in comparison provides program and data storage that is slower to access but offers larger capacity. Examples include external hard drives, portable flash drives, CDs, and DVDs. These devices and media must be either plugged in or inserted into a computer in order to be accessed by the system. Since secondary storage technology is not always connected to the computer, it is commonly used for backing up data. The term storage is often used to describe secondary memory. Secondary memory stores a large amount of data at lesser cost per byte than primary memory; this makes secondary storage about two orders of magnitude less expensive than primary storage. There are two main types of semiconductor memory: volatile and nonvolatile. Examples of non-volatile memory are ‘Flash’ memory (sometimes used as secondary, sometimes primary computer memory) and ROM/PROM/EPROM/EEPROM memory (used for firmware such as boot programs). Examples of volatile memory are primary memory (typically dynamic RAM, DRAM), and fast CPU cache memory (typically static RAM, SRAM, which is fast but energy-consuming and offer lower memory capacity per are a unit than DRAM). Non-volatile memory technologies in Si-based electronics date back to the 1990s. Flash memory is widely used in consumer electronic products such as cellphones and music players and NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. The rapid increase of leakage currents in Silicon CMOS transistors with scaling poses a big challenge for the integration of SRAM memories. There is also the case of susceptibility to read/write failure with low power schemes. As a result of this, over the past decade, there has been an extensive pooling of time, resources and effort towards developing emerging memory technologies like Resistive RAM (ReRAM/RRAM), STT-MRAM, Domain Wall Memory and Phase Change Memory(PRAM). Emerging non-volatile memory technologies promise new memories to store more data at less cost than the expensive-to build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. These new memory technologies combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the non-volatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. The research and information on these Non-Volatile Memory (NVM) technologies has matured over the last decade. These NVMs are now being explored thoroughly nowadays as viable replacements for conventional SRAM based memories even for the higher levels of the memory hierarchy. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional(3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years...En el campo de la informática, el término ‘memoria’ se refiere generalmente a dispositivos que son usados para almacenar información que posteriormente será usada en diversos dispositivos, desde computadoras personales (PC), móviles, dispositivos inteligentes, etc. La memoria principal del sistema se utiliza para almacenar los datos e instrucciones de los procesos que se encuentre en ejecución, por lo que se requiere que funcionen a alta velocidad (por ejemplo, DRAM). La memoria principal está implementada habitualmente mediante memorias semiconductoras direccionables, siendo DRAM y SRAM los principales exponentes. Por otro lado, la memoria auxiliar o secundaria proporciona almacenaje(para ficheros, por ejemplo); es más lenta pero ofrece una mayor capacidad. Ejemplos típicos de memoria secundaria son discos duros, memorias flash portables, CDs y DVDs. Debido a que estos dispositivos no necesitan estar conectados a la computadora de forma permanente, son muy utilizados para almacenar copias de seguridad. La memoria secundaria almacena una gran cantidad de datos aun coste menor por bit que la memoria principal, siendo habitualmente dos órdenes de magnitud más barata que la memoria primaria. Existen dos tipos de memorias de tipo semiconductor: volátiles y no volátiles. Ejemplos de memorias no volátiles son las memorias Flash (algunas veces usadas como memoria secundaria y otras veces como memoria principal) y memorias ROM/PROM/EPROM/EEPROM (usadas para firmware como programas de arranque). Ejemplos de memoria volátil son las memorias DRAM (RAM dinámica), actualmente la opción predominante a la hora de implementar la memoria principal, y las memorias SRAM (RAM estática) más rápida y costosa, utilizada para los diferentes niveles de cache. Las tecnologías de memorias no volátiles basadas en electrónica de silicio se remontan a la década de1990. Una variante de memoria de almacenaje por carga denominada como memoria Flash es mundialmente usada en productos electrónicos de consumo como telefonía móvil y reproductores de música mientras NAND Flash solid state disks(SSDs) están progresivamente desplazando a los dispositivos de disco duro como principal unidad de almacenamiento en computadoras portátiles, de escritorio e incluso en centros de datos. En la actualidad, hay varios factores que amenazan la actual predominancia de memorias semiconductoras basadas en cargas (capacitivas). Por un lado, se está alcanzando el límite de integración de las memorias Flash, lo que compromete su escalado en el medio plazo. Por otra parte, el fuerte incremento de las corrientes de fuga de los transistores de silicio CMOS actuales, supone un enorme desafío para la integración de memorias SRAM. Asimismo, estas memorias son cada vez más susceptibles a fallos de lectura/escritura en diseños de bajo consumo. Como resultado de estos problemas, que se agravan con cada nueva generación tecnológica, en los últimos años se han intensificado los esfuerzos para desarrollar nuevas tecnologías que reemplacen o al menos complementen a las actuales. Los transistores de efecto campo eléctrico ferroso (FeFET en sus siglas en inglés) se consideran una de las alternativas más prometedores para sustituir tanto a Flash (por su mayor densidad) como a DRAM (por su mayor velocidad), pero aún está en una fase muy inicial de su desarrollo. Hay otras tecnologías algo más maduras, en el ámbito de las memorias RAM resistivas, entre las que cabe destacar ReRAM (o RRAM), STT-RAM, Domain Wall Memory y Phase Change Memory (PRAM)...Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu

The Efficacy of Programming Energy Controlled Switching in Resistive Random Access Memory (RRAM)

Current state-of-the-art memory technologies such as FLASH, Static Random Access Memory (SRAM) and Dynamic RAM (DRAM) are based on charge storage. The semiconductor industry has relied on cell miniaturization to increase the performance and density of memory technology, while simultaneously decreasing the cost per bit. However, this approach is not sustainable because the charge-storage mechanism is reaching a fundamental scaling limit. Although stack engineering and 3D integration solutions can delay this limit, alternate strategies based on non-charge storage mechanisms for memory have been introduced and are being actively pursued. Resistive Random Access Memory (RRAM) has emerged as one of the leading candidates for future high density non-volatile memory. The superior scalability of RRAMs is based on the highly localized active switching region and filamentary conductive path. Coupled with its simple structure and compatibility with complementary metal oxide semiconductor (CMOS) processes; RRAM cells have demonstrated switching performance comparable to volatile memory technologies such as DRAMs and SRAMs. However, there are two serious barriers to RRAM commercialization. The first is the variability of the resistance state which is associated with the inherent randomness of the resistive switching mechanism. The second is the filamentary nature of the conductive path which makes it susceptible to noise. In this experimental thesis, a novel program-verify (P-V) technique was developed with the objective to specifically address the programming errors and to provide solutions to the most challenging issues associated with these intrinsic failures in current RRAM technology. The technique, called Compliance-free Ultra-short Smart Pulse Programming (CUSPP), utilizes sub-nanosecond pulses in a compliance-free setup to minimize the programming energy delivered per pulse. In order to demonstrate CUSPP, a custom-built picosecond pulse generator and feedback control circuit was designed. We achieved high (108 cycles) endurance with state verification for each cycle and established high-speed performance, such as 100 ps write/erase speed and 500 kHz cycling rate of HfO2-based RRAM cells. We also investigate switching failure and the short-term instability of the RRAM using CUSPP

Towards Energy-Efficient and Reliable Computing: From Highly-Scaled CMOS Devices to Resistive Memories

The continuous increase in transistor density based on Moore\u27s Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation. Based on the results, using the 15nm technology offers 4-times less energy and 3-fold smaller footprint. New challenges also arise, such as relative proportion of leakage power in standby mode that can be addressed by post-CMOS technologies. Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, and assessed herein. Cost and suitability metrics assessed include the area of nanomagmetic and CMOS components per bit, access time and complexity, Sense Margin (SM), and energy or power consumption costs versus resiliency benefits. In an attempt to further improve the Process Variation (PV) immunity of the Sense Amplifiers (SAs), a new SA has been introduced called Adaptive Sense Amplifier (ASA). ASA can benefit from low Bit Error Rate (BER) and low Energy Delay Product (EDP) by combining the properties of two of the commonly used SAs, Pre-Charge Sense Amplifier (PCSA) and Separated Pre-Charge Sense Amplifier (SPCSA). ASA can operate in either PCSA or SPCSA mode based on the requirements of the circuit such as energy efficiency or reliability. Then, ASA is utilized to propose a novel approach to actually leverage the PV in Non-Volatile Memory (NVM) arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time

Nanoscale resistive switching memory devices: a review

In this review the different concepts of nanoscale resistive switching memory devices are described and classified according to their I–V behaviour and the underlying physical switching mechanisms. By means of the most important representative devices, the current state of electrical performance characteristics is illuminated in-depth. Moreover, the ability of resistive switching devices to be integrated into state-of-the-art CMOS circuits under the additional consideration with a suitable selector device for memory array operation is assessed. From this analysis, and by factoring in the maturity of the different concepts, a ranking methodology for application of the nanoscale resistive switching memory devices in the memory landscape is derived. Finally, the suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed

전자 장치 내 국부적 전계 향상을 위한 나노 구조체

학위논문(박사) -- 서울대학교대학원 : 공과대학 화학생물공학부, 2021.8. 조재영.The goal of this dissertation is to investigate effect of nanostructures for local electric field enhancement in electronic devices and to provide experimental and theoretical bases for their practical use. Resistive random access memory (RRAM) is a data storage device that can be modulated its resistance states by external electrical stimuli. The electric field generated by the applied potential difference between the two electrodes acts as the driving force to switch the resistance states, so controlling the electric field within the device can lead to improved operational performance and reliability of the device. Even though considerable progress has been made through significant efforts to control the electric field within the device, selectively enhancing the electric field in the intended position for stable and uniform resistive switching behavior is still challenging. Engineered metal structures in the RRAM can efficiently manipulate the electric field. As the radius of the metal structures decreases, the charge density increases, generating electric field enhancements in confined region. To minimize the radius of the metal structure and thus to greatly increase the electric field in a local area, we introduced a nanoscale metal structure into the RRAM. First, pyramid-structured metal electrode with a sharp tip was used to achieve a tip-enhanced electric field, and the effect of the enhanced electric field on the resistive switching behaviors of the device was investigated. Based on numerical simulation and experimental results, we confirmed that pyramidal electrode with a tip radius of tens of nanometers can selectively enhance the electric field at the tip. The tip-enhanced electric field can facilitate the thermochemical reaction in transition metal oxide-based RRAMs and efficiency of charge injection and transport in organic-based RRAMs, as well as provide position selectivity during formation of conductive filament. The resulting RRAM exhibited reliable resistive switching behavior and highly improved device performance compared with conventional RRAM with planar electrode. As another approach to enhance the electric field within the resistive switching layer, we prepared spherical nanostructures via self-assembled block copolymer (BCP)/metal compound micelles. BCP and metal precursors were dissolved in aqueous media for use as BCP/metal compound micelles. These micelles were used as complementary resistive switch (CRS) layers of the memory device and the mechanism of CRS behavior was investigated. The spherical metal nanostructures can improve the electric fields, promoting a resistive switching mechanism based on electrochemical metallization. The resulting CRS memory exhibited reliable resistive switching behavior with four distinct threshold voltages in both cycle-to-cycle and cell-to-cell tests. Also, the conduction and resistive switching mechanism are experimentally demonstrated through the the analysis of the current–voltage data plot and detemination of the temperature coefficient of resistance. Overall, we pursued efficient engineering of metal nanostructures capable of manipulating electric fields for improving the operational performance and reliability of memory devices. There is no doubt that the commercialized RRAM will become popular in the near future after overcoming all the challenges of RRAM through continuous interest and research. We believe that these results will not only contribute to the significant advancement of all electronic devices, including RRAM, but will also help promote research activities in the electronic device field.본 논문의 목적은 나노 구조체를 통한 전자 장치 내 국부적 전계 향상 효과를 조사하고, 이의 실제 사용을 위한 실험 및 이론적 기반을 제공하는 것이다. 저항변화메모리 (resistive random access memory) 는 외부 전기 자극에 의해 저항 상태를 변화 시킬 수 있는 데이터 저장 장치이다. 두 전극 사이에 인가된 전위차에 의해 생성된 전기장은 저항 상태를 전환시키는 구동력으로써 작용하므로, 전자 장치 내에서 전기장을 제어하면 장치의 성능과 신뢰성을 향상시킬 수 있다. 장치 내에서 전기장을 제어하려는 많은 노력을 통해 상당한 진전이 있었지만, 안정적이고 균일한 저항 변화 거동을 위해 의도된 위치에서 전기장을 선택적으로 향상시키는 일은 아직 도전적 과제이다. 구조화된 금속을 저항변화메모리에 접목시킴으로써 전기장을 효율적으로 조작할 수 있다. 금속 구조체의 반경이 감소함에 따라 전하 밀도가 증가하여 국부적 영역에서 전기장이 향상된다. 이 논문에서는 금속 구조체의 반경을 최소화하여 국부적으로 전기장을 크게 향상시키기 위해 저항변화메모리에 나노스케일의 금속 구조체를 도입하였다. 첫 번째로, 팁 강화 (tip-enhanced) 전기장 효과를 달성하기 위해 날카로운 팁을 가지는 피라미드 금속 구조체를 전극으로 사용하였으며, 강화된 전기장이 소자의 저항 변화 거동에 미치는 영향을 조사하였다. 유한요소모델링과 실험결과를 바탕으로, 수십 나노 미터의 팁 반경을 가지는 피라미드 구조체 전극이 팁 부근에서 전기장을 국소적으로 향상시킬 수 있음을 확인하였다. 팁 강화 전기장은 전이 금속 산화물-기반 저항변화메모리에서 열화학 (thermochemical) 반응을 촉진시키고 유기-기반 저항변화메모리에서 전하 주입 (charge injection) 및 수송 (transport) 효율성을 향상시킬 뿐 아니라, 선택적인 위치에서만 전도성 필라멘트 (conductive filament)를 형성시킬 수 있었다. 그 결과 피라미드 구조체 저항변화메모리는 종래의 평판 구조체 저항변화메모리에 비해 안정적인 저항 변화 거동과 향상된 장치 성능을 보여주었다. 저항 변화 층 내의 전기장을 향상시키기 위한 또 다른 접근법으로, 자기조립 (self-assembled)된 블록공중합체 (block copolymer)/금속 복합체 미셀 (micelle)을 이용하여 구형의 나노구조체를 소자의 중간층으로 도입하였다. 블록공중합체 및 금속전구체를 복합체 미셀로 사용하기 위해 선택적 용매에 용해시켰다. 해당 미셀을 메모리 소자의 상보적 저항 변화 (complementary resistive switch) 층으로 사용하였으며, 상보적 저항 변화 거동의 메커니즘을 조사하였다. 구형의 금속 나노구조체는 전기장을 향상시켜 전기화학적 금속화 (electrochemical metallization)에 기반한 저항 변화 메커니즘을 촉진시킬 수 있었다. 그 결과 상보적 저항 변화 메모리는 사이클 및 셀간 반복 시험 모두에서 4개의 임계 전압으로 안정적인 저항 변화 동작을 나타내었다. 또한 전류-전압 자료 플롯 (plot) 분석과 저항의 온도 계수 결정을 통해 장치의 전도 및 저항 변화 메커니즘을 실험적으로 입증하였다. 전반적으로 본 논문에서는 장치 내 전기장을 증폭시킬 수 있는 금속 나노구조체의 효율적인 엔지니어링을 통해 메모리 장치의 성능과 신뢰성 향상을 추구하였다. 지속적인 관심과 연구를 통해 저항변화메모리의 모든 과제를 극복한 후, 상용화된 저항변화메모리가 가까운 미래에 대중화될 것임을 믿어 의심치 않는다. 우리는 이 결과가 저항변화메모리를 포함한 모든 전자 장치의 획기적인 발전에 기여할 뿐만 아니라 전자 장치 분야의 연구 활동을 촉진하는 데에도 도움이 될 것이라고 믿는다.Chapter 1. Introduction 1 1.1. Background 1 1.1.1. Necessity of new memory devices 1 1.1.2. Resistive random access memory 2 1.2. Motivation 4 1.3. Dissertation Overview 6 1.4. References 9 Chapter 2. Tip-Enhanced Electric Field-Driven Efficient Charge Injection and Transport in Organic Material-Based Resistive Memories 19 2.1. Introduction 21 2.2. Experimental 24 2.3. Results and Discussion 27 2.4. Conclusions 37 2.5. References 38 Chapter 3. Facilitation of the Thermochemical Mechanism in NiO-Based Resistive Switching Memories via Tip-Enhanced Electric Fields 52 3.1. Introduction 54 3.2. Experimental 57 3.3. Results and Discussion 60 3.4. Conclusions 66 3.5. References 67 Chapter 4. Facile Achievement of Complementary Resistive Switching Behaviors via Self-Assembled Block Copolymer Micelles 82 4.1. Introduction 83 4.2. Experimental 86 4.3. Results and Discussion 89 4.4. Conclusions 96 4.5. References 97 Chapter 5. Conclusion 109 Abstract in Korean 112박

Review and perspective on ferroelectric HfO₂-based thin films for memory applications

The ferroelectricity in fluorite-structure oxides such as hafnia and zirconia has attracted increasing interest since 2011. They have various advantages such as Si-based complementary metal oxide semiconductor-compatibility, matured deposition techniques, a low dielectric constant and the resulting decreased depolarization field, and stronger resistance to hydrogen annealing. However, the wake-up effect, imprint, and insufficient endurance are remaining reliability issues. Therefore, this paper reviews two major aspects: the advantages of fluorite-structure ferroelectrics for memory applications are reviewed from a material’s point of view, and the critical issues of wake-up effect and insufficient endurance are examined, and potential solutions are subsequently discussed

Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach

Energy consumption becomes the most critical limitation on the performance of nowadays embedded system designs. On-chip memories due to major contribution in overall system energy consumption are always significant issue for embedded systems. Using conventional memory technologies in future designs in nano-scale era causes a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies are promising replacement for conventional memory structure in embedded systems due to its attractive characteristics such as near-zero leakage power, high density and non-volatility. Recent advantages of NVM technologies can significantly mitigate the issue of memory leakage power. However, they introduce new challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system to minimize energy consumption for 3D embedded chip-multiprocessors (eCMP). For reaching this target, we present a convex optimization-based model to distribute data blocks between SRAM and NVM banks based on data access pattern derived by compiler. Our compiler-assisted hybrid memory architecture can achieve up to 51.28 times improvement in lifetime. In addition, experimental results show that our proposed method reduce energy consumption by 56% on average compared to the traditional memory design where single technology is used. © 2015 IEEE