Design and Implementation of Area and Power Efficient Low Power VLSI Circuits through Simple Byte Compression with Encoding Technique

Transition activity is one of the major factors for power dissipation in Low power VLSI circuits due to charging and discharging of internal node capacitances. Power dissipation is reduced through minimizing the transition activity by using proper coding techniques. In this paper Multi coding technique is implemented to reduce the transition activity up to 58.26%. Speed of data transmission basically depends on the number of bits transmitted through bus. When handling data for large applications huge storage space is required for processing, storing and transferring information. Data compression is an algorithm to reduce the number of bits required to represent information in a compact form. Here simple byte compression technique is implemented to achieve a lossless data compression. This compression algorithm also reduces the encoder computational complexity when handling huge bits of information. Simple byte compression technique improves the compression ratio up to 62.5%. As a cumulative effort of Simple byte compression with Multi coding techniques minimize area and power dissipation in low power VLSI circuits

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Low Power Design Methodology

Due to widespread application of portable electronic devices and the evaluation of microelectronic technology, power dissipation has become a critical parameter in low power VLSI circuit designs. In emerging VLSI technology, the circuit complexity and high speed imply significant increase in the power consumption. In low power CMOS VLSI circuits, the energy dissipation is caused by charging and discharging of internal node capacitances due to transition activity, which is one of the major factors that also affect the dynamic power dissipation. The reduction in power, area and the improvement of speed require optimization at all levels of design procedures. Here various design methodologies are discussed to achieve our required low power design concepts

A Unified Codec Scheme for reduction of Area and Crosstalk in RC and RLC Modeled Interconnects using both Bus Encoding and Shielding Insertion Technique

This paper presents a unified codec scheme for reduction of area and crosstalk in RC and RLC modeled interconnects using both bus encoding and shielding insertion technique. It is based upon bus invert method and focuses on 4 bit coupled lines. Previously used codec scheme focused independently on either RC or RLC models and they considered coupling between 5 bit coupled lines i.e. 4 bit data lines and 1 bit control line. However, our proposed codec scheme focuses on all types of couplings i.e. Type-0 to Type-4 and demonstrates an overall reduction in area as well as crosstalk considering coupling between 4 bit coupled lines and isolating the control signal using redundant shielding thus reducing the cases of coupling drastically. The proposed work has been implemented using both Semi Custom and Full Custom design approaches. The model has been described, synthesized and simulated in hardware description language VHDL along with its FPGA implementation. The power consumption has been calculated using Xpower tool of Xilinx. Same model has also been implemented using Cadence Virtuoso Analog Design Suite in 0.18um CMOS technology and the corresponding power, delay and area has been computed. The proposed scheme demonstrates an overall reduction of 76.68% in crosstalk delay and 56.33% in chip area and transistor count. 79.58% power reduction is achieved in full-custom design implementation as compared to semi-custom design implementation.DOI:http://dx.doi.org/10.11591/ijece.v3i4.317

Energy macro-model for on chip interconnection buses

This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. With this model we are be able to evaluate the energy metrics for the bus under a certain traffic and information coding.Peer Reviewe

Comparative Analysis of Spatio and Viterbi Encoding and Decoding Techniques in Hardware Description Language

The paper focuses on the design and synthesis of hardware chip for Spatio and Viterbi encoding and decoding techniques. Both techniques are used for digital data encoding and decoding in transmitter and receiver respectively. These techniques are used for error control coding found in convolution codes. Spatio coding is also used to eliminate crosstalk among interconnect wires, thereby reducing delay. The encoded data is in packet form may be of 2018;N2019; bits. Data is decoded at different clock pluses at which it is encoded. A comparative analysis is done for hardware parameter, timing parameters and device utilization. Design is implemented in Xilinx 14.2 VHDL software, and functional simulation was carried out in Modelsim 10.1 b, student edition. Hardware parameters such as size cost and timings are extracted from the design code

Analysis and implementation of charge recycling for deep sub-micron buses

ABSTRACT : Charge recycling has been proposed as a strategy to reduce the power dissipation in data buses. Previous work in this area was based on simplified bus models that ignored the coupling between the lines. Here we propose a new Charge Recycling Technique (CRT) appropriate for sub-micron technologies. CRT is analyzed mathematically using a bus energy model that captures the energy loss due to strong line to line capacitive coupling. In theory CRT can result to energy reduction of a factor of 2. It becomes even more energy efficient when combined with Bus Invert coding (Stan '97