Principles of Neuromorphic Photonics

In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast

Small business innovation research. Abstracts of completed 1987 phase 1 projects

Non-proprietary summaries of Phase 1 Small Business Innovation Research (SBIR) projects supported by NASA in the 1987 program year are given. Work in the areas of aeronautical propulsion, aerodynamics, acoustics, aircraft systems, materials and structures, teleoperators and robotics, computer sciences, information systems, spacecraft systems, spacecraft power supplies, spacecraft propulsion, bioastronautics, satellite communication, and space processing are covered

Physical Layer Modeling and Optimization of Silicon Photonic Interconnection Networks

The progressive blooming of silicon photonics technology (SiP) has indicated that optical interconnects may substitute the electrical wires for data movement over short distances in the future. Silicon Photonics platform has been the subject of intensive research for more than a decade now and its prospects continue to emerge as it enjoys the maturity of CMOS manufacturing industry. SiP foundries all over the world and particularly in the US (AIM Photonics) have been developing reliable photonic design kits (PDKs) that include fundamental SiP building blocks such as wavelength selective modulators and tunable filters. Microring resonators (MRR) are hailed as the most compact devices that can perform both modulation and demodulation in a wavelength division multiplexed (WDM) transceiver design. Although the use of WDM can reduce the number of fibers carrying data, it also makes the design of transceivers challenging. It is probably acceptable to achieve compactness at the expense of somewhat higher transceiver cost and power consumption. Nevertheless, these two metrics should remain close to their roadmap values for Datacom applications. An increase of an order of magnitude is clearly not acceptable. For example costs relative to bandwidth for an optical link in a data center interconnect will have to decrease from the current $5/Gbps down to <$1/Gbps. Additionally, the transceiver itself must remain compact. The optical properties of SiP devices are subject to various design considerations, operation conditions, and optimization procedures. In this thesis, the general goal is to develop mathematical models that can accurately describe the thermo-optical and electro-optical behavior of individual SiP devices and then use these models to perform optimization on the parameters of such devices to maximize the capabilities of photonic links or photonic switch fabrics for datacom applications. In Chapter 1, Introduction, we first provide an overview of the current state of the optical transceivers for data centers and datacom applications. Four main categories for optical interfaces (Pluggable transceivers, On-board optics, Co-packaged optics, monolithic integration) are briefly discussed. The structure of a silicon photonic link is also briefly introduced. Then the direction is shifted towards optical switching technologies where various technologies such as free space MEMS, liquid crystal on silicon (LCOS), SOA-based switches, and silicon-based switches are explored. In Chapter 2, Silicon Photonic Waveguides, we present an extensive study of the silicon-on-insulator (SOI) waveguides that are the basic building blocks of all of the SiP devices. The dispersion of Si and SiO2 is modeled with Sellmiere equation for the wavelength range 1500–1600 nm and then is used to calculate the TE and TM modes of a 2D slab waveguide. There are two reasons that 2D waveguides are studied: first, the modes of these waveguides have closed form solutions and the modes of 3D waveguides can be approximated from 2D waveguides based on the effective index method. Second, when the coupling of waveguides is studied and the concept of curvature function of coupling is developed, the coupled modes of 2D waveguides are used to show that this approach has some inherent small error due to the discretization of the nonuniform coupling. This chapter finishes by describing the coefficients of the sensitivity of optical modes of the waveguides to the geometrical and material parameters. Perturbation theory is briefly presented as a way to analytically examine the impact of small perturbations on the effective index of the modes. In Chapter 3, Compact Modeling Approach, the concept of scattering matrix of a multi-port silicon photonic device is presented. The elements of the S-matrix are complex numbers that relate the amplitude and phase relationships of the optical models in the input and output ports. Based on the scattering matrix modeling of silicon photonics devices, two methods of solving photonic circuits are developed: the first one is based on the iteration for linear circuits. The second approach is based on the construction of an equivalent signal flow graph (SFG) for the circuit. We show that the SFG approach is very efficient for circuits involving microring resonator structures. Not only SFG can provide the solution for the transmission, it also provides the signal paths and the closed-form solution based on the Mason’s graph formula. We also show how the SFG method can be utilized to formulate the backscattering effects inside a ring resonator. In Chapter 4, Scalability of Silicon Photonic Switch Fabrics, we develop the models for electro-optic Mach-Zehnder switch elements (2×2). For the electro-optic properties, the empirical Soref’s equations are used to characterize how the loss and index of silicon changes when the charge carrier density is changed. We then use our photonic circuit solver based on the iteration method to find accurate result of light propagation in large-scale switch topologies (e.g. 4×4, and 8×8). The concept of advanced path mapping based on physical layer evaluation of the switch fabric is introduced and used to develop the optimum routing tables for 4×4 and 8×8 Benes switch topologies. In Chapter 5, Design space of Microring Resonators, we introduce the concept of curvature function of coupling to mathematically characterize the coupling coefficient of a ring resonator to a waveguide as a function of the geometrical parameters (ring radius, coupling gap, width and height of waveguides) and the wavelength. Extensive 2D and 3D FDTD simulations are carried out to validate our modeling approach. Experimental demonstrations are also used to not only further validate our modeling of coupling, but also to extract an empirical power-law model for the bending loss of the ring resonators as a function the radius. By combining these models, we for the first time present a full characterization of the design space of microring resonators. Moreover, the value of this discussion will be further apparent when the scalability of a silicon photonic link is studied. We will show that the FSR of the rings determines the optical bandwidth but it also impacts the properties of the ring resonators. In Chapter 6, Thermo-optic Efficiency of Microheaters, we develop analytical models for the thermo-optic properties of SiP waveguides. For the thermo-optic properties, the concept of thermal impulse response is mathematically developed for integrated micro-heaters. The thermal impulse response is a key function that determines the tradeoff between heating efficiency and heating speed (thermal bandwidth), as well as allows us to predict the pulse-width-modulation (PWM) optical response of the heater-waveguide system. One of the motivations behind this study was to find the highest possible efficiency for thermal tuning of microring resonators to use it in the evaluation of the energy consumption of a photonic link. The results indicate 2 nm/mW which is in agreement with the trends that we see in the literature. In Chapter 7, Crosstalk Penalty, we theoretically and experimentally investigate the optical crosstalk effects in microring-based silicon photonic interconnects. Both inter-channel crosstalk and intra-channel crosstalk are investigated and approximate equations are developed for their corresponding power penalties. Inclusion of the inter-channel crosstalk is an important part of our final analysis of a silicon photonic link. In Chapter 8, Scalability of Silicon Photonic Links, we present the analysis of a WDM silicon photonics point-to-point link based on microring modulators and microring wavelength filters. Our approach is based on the power penalty analysis of non-return-to-zero (NRZ) signals and Gaussian noise statistics. All the necessary equations for the optical power penalty calculations are presented for microring modulators and filters. The first part of the analysis is based on various ideal assumptions which lead to a maximum capacity of 2.1 Tb/s for the link. The second part of the analysis is carried out with more realistic assumptions on the photonic elements in the link, culminating in a maximum throughput of 800 Gb/s. We also provide estimations of the energy/bit metric of such links based on the optimized models of electronic circuits in 65 nm CMOS technology

Architectural Exploration and Design Methodologies of Photonic Interconnection Networks

Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on- and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this work, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment called PhoenixSim. Next, we leverage PhoenixSim for the study of chip-scale photonic networks. We examine several photonic networks through the synergistic study of both physical-layer metrics and system-level metrics. This holistic analysis method enables us to provide deeper insight into architecture scalability since it considers insertion loss, crosstalk, and power dissipation. In addition to these novel physical-layer metrics, traditional system-level metrics of bandwidth and latency are also obtained. Lastly, we propose a novel routing architecture known as wavelength-selective spatial routing. This routing architecture is analogous to electronic virtual channels since it enables the transmission of multiple logical optical channels through a single physical plane (i.e. the waveguides). The available wavelength channels are partitioned into separate groups, and each group is routed independently in the network. Each partition is spectrally multiplexed, as opposed to temporally multiplexed in the electronic case. The wavelength-selective spatial routing technique benefits network designers by provider lower contention and increased path diversity