Non-power-of-Two FFTs: Exploring the Flexibility of the Montium TP

Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class of non-power-of-two FFTs to discover the limitations and Flexibility of the Montium TP for less regular algorithms. A non-power-of-two FFT is less regular compared to a traditional power-of-two FFT. The results of the implementation show the processing time, accuracy, energy consumption and Flexibility of the implementation

Is FFT Fast Enough for Beyond-5G Communications?

This paper studies the impact of computational complexity on the throughput limits of different Discrete Fourier Transform (DFT) algorithms (such as FFT and straightforward DFT) in the context of OFDM-based waveforms. Based on the spectro-computational complexity (SC) analysis, it is verified that the complexity of an $N$-point FFT grows faster than the number of bits in the OFDM symbol. Thus, the useful throughput of FFT nullifies on $N$. Also, because FFT demands $N$ to be a power of two $2^i$ ($i>0$), the spectrum widening leads to an exponential complexity on $i$, i.e. $O(2^ii)$. To overcome these limitations, we consider the alternative frequency-time transform formulation of Vector OFDM (V-OFDM), in which an $N$-point FFT is replaced by $N/L$ ($L$$>$$0$) smaller $L$-point FFTs to mitigate the cyclic prefix overhead of OFDM. Building on that, we replace FFT by the straightforward DFT algorithm to release the V-OFDM parameters from growing as powers of two and to benefit from flexible numerology (e.g., $L=3$, $N=156$). Besides, by setting $L$ to $\Theta(1)$, the resulting solution can run linearly on $N$ (rather than exponentially on $i$) while sustaining a non null throughput as $N$ grows.Comment: This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessibl

A common operator for FFT and FEC decoding

International audienceIn the Software Radio context, the parametrization is becoming an important topic especially when it comes to multistandard designs. This paper capitalizes on the Common Operator technique to present new common structures for the FFT and FEC decoding algorithms. A key benefit of exhibiting common operators is the regular architecture it brings when implemented in a Common Operator Bank (COB). This regularity makes the architecture open to future function mapping and adapted to accommodated silicon technology variability through dependable design

Effects of Fixed Point FFT Implementation of Wireless LAN

With the rapid growth of digital wireless communication in recent years, the need for high speed mobile data transmission has increased. New modulation techniques are being implemented to keep with the desire more communication capacity. Processing power has increased to a point where orthogonal frequency division multiplexing (OFDM) has become feasible and economical. Since many wireless communication systems being developed use OFDM, it is a worthwhile research topic. Some examples of applications using OFDM include Digital subscriber line (DSL), Digital Audio Broadcasting (DAB), High definition television (HDTV) broadcasting, IEEE 802.11 (wireless networking standard).OFDM is a strong candidate and has been suggested or standardized in high speed communication systems. This thesis analyzes the factor that affects the OFDM performance. The performance of OFDM was assessed by using computer simulations performed using Matlab.it was simulated under Additive white Gaussian noise (AWGN) channel conditions for different modulation schemes like binary phase shift keying (BPSK), Quadrature phase shift keying (QPSK), 16-Quadrature amplitude modulation (16-QAM), 64-Quadrature amplitude modulation (64-QAM) which are used in wireless LAN for achieving high data rates. One key component in OFDM based systems is inverse fast Fourier transform/fast Fourier transform (IFFT/FFT) computation, which performs the efficient modulation/demodulation. This block consumes large resources in terms of computational power.this thesis analyzes, different IFFT/FFT implementation on performance of OFDM communication system. Here 64-point IFFT/ FFT is used. FFT is a complex function whose computational accuracy, hardware size and processing speed depend on the type of arithmetic format used to implement it. Due to non-linearity of FFT its computational accuracy is not easy to calculate theoretically. The simulation carried out here, measure the effects of fixed point FFT on the performance of OFDM. Comparison has been made between bit error rate of OFDM using fixed point IFFT/FFT and a floating point IFFT/FFT. Simulation tests were made for different integer part lengths, fractional part lengths by limiting the input word lengths to 16 bits and found the suitable combination of integer part lengths and fractional part lengths which can achieve the best bit error rate (BER) performance with respect to floating point performance. Extensive computer simulations show that fixed point computation provides very near result as floating point if the delay parameter is suitably selected

Digital and Mixed Domain Hardware Reduction Algorithms and Implementations for Massive MIMO

Emerging 5G and 6G based wireless communications systems largely rely on multiple-input-multiple-output (MIMO) systems to reduce inherently extensive path losses, facilitate high data rates, and high spatial diversity. Massive MIMO systems used in mmWave and sub-THz applications consists of hundreds perhaps thousands of antenna elements at base stations. Digital beamforming techniques provide the highest flexibility and better degrees of freedom for phased antenna arrays as compared to its analog and hybrid alternatives but has the highest hardware complexity. Conventional digital beamformers at the receiver require a dedicated analog to digital converter (ADC) for every antenna element, leading to ADCs for elements. The number of ADCs is the key deterministic factor for the power consumption of an antenna array system. The digital hardware consists of fast Fourier transform (FFT) cores with a multiplier complexity of (N log2N) for an element system to generate multiple beams. It is required to reduce the mixed and digital hardware complexities in MIMO systems to reduce the cost and the power consumption, while maintaining high performance. The well-known concept has been in use for ADCs to achieve reduced complexities. An extension of the architecture to multi-dimensional domain is explored in this dissertation to implement a single port ADC to replace ADCs in an element system, using the correlation of received signals in the spatial domain. This concept has applications in conventional uniform linear arrays (ULAs) as well as in focal plane array (FPA) receivers. Our analysis has shown that sparsity in the spatio-temporal frequency domain can be exploited to reduce the number of ADCs from N to where . By using the limited field of view of practical antennas, multiple sub-arrays are combined without interferences to achieve a factor of K increment in the information carrying capacity of the ADC systems. Applications of this concept include ULAs and rectangular array systems. Experimental verifications were done for a element, 1.8 - 2.1 GHz wideband array system to sample using ADCs. This dissertation proposes that frequency division multiplexing (FDM) receiver outputs at an intermediate frequency (IF) can pack multiple (M) narrowband channels with a guard band to avoid interferences. The combined output is then sampled using a single wideband ADC and baseband channels are retrieved in the digital domain. Measurement results were obtained by employing a element, 28 GHz antenna array system to combine channels together to achieve a 75% reduction of ADC requirement. Implementation of FFT cores in the digital domain is not always exact because of the finite precision. Therefore, this dissertation explores the possibility of approximating the discrete Fourier transform (DFT) matrix to achieve reduced hardware complexities at an allowable cost of accuracy. A point approximate DFT (ADFT) core was implemented on digital hardware using radix-32 to achieve savings in cost, size, weight and power (C-SWaP) and synthesized for ASIC at 45-nm technology

Algorithms and Circuits for Analog-Digital Hybrid Multibeam Arrays

Fifth generation (5G) and beyond wireless communication systems will rely heavily on larger antenna arrays combined with beamforming to mitigate the high free-space path-loss that prevails in millimeter-wave (mmW) and above frequencies. Sharp beams that can support wide bandwidths are desired both at the transmitter and the receiver to leverage the glut of bandwidth available at these frequency bands. Further, multiple simultaneous sharp beams are imperative for such systems to exploit mmW/sub-THz wireless channels using multiple reflected paths simultaneously. Therefore, multibeam antenna arrays that can support wider bandwidths are a key enabler for 5G and beyond systems. In general, N-beam systems using N-element antenna arrays will involve circuit complexities of the order of N2. This dissertation investigates new analog, digital and hybrid low complexity multibeam beamforming algorithms and circuits for reducing the associated high size, weight, and power (SWaP) complexities in larger multibeam arrays. The research efforts on the digital beamforming aspect propose the use of a new class of discrete Fourier transform (DFT) approximations for multibeam generation to eliminate the need for digital multipliers in the beamforming circuitry. For this, 8-, 16- and 32-beam multiplierless multibeam algorithms have been proposed for uniform linear array applications. A 2.4 GHz 16-element array receiver setup and a 5.8 GHz 32-element array receiver system which use field programmable gate arrays (FPGAs) as digital backend have been built for real-time experimental verification of the digital multiplierless algorithms. The multiplierless algorithms have been experimentally verified by digitally measuring beams. It has been shown that the measured beams from the multiplierless algorithms are in good agreement with the exact counterpart algorithms. Analog realizations of the proposed approximate DFT transforms have also been investigated leading to low-complex, high bandwidth circuits in CMOS. Further, a novel approach for reducing the circuit complexity of analog true-time delay (TTD) N-beam beamforming networks using N-element arrays has been proposed for wideband squint-free operation. A sparse factorization of the N-beam delay Vandermonde beamforming matrix is used to reduce the total amount of TTD elements that are needed for obtaining N number of beams in a wideband array. The method has been verified using measured responses of CMOS all-pass filters (APFs). The wideband squint-free multibeam algorithm is also used to propose a new low-complexity hybrid beamforming architecture targeting future 5G mmW systems. Apart from that, the dissertation also explores multibeam beamforming architectures for uniform circular arrays (UCAs). An algorithm having N log N circuit complexity for simultaneous generation of N-beams in an N-element UCA is explored and verified