Design and analysis of efficient QCA reversible adders

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architecture

A review on reversible logic gates

In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.   Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic

A thermally aware performance analysis of quantum cellular automata logic gates

The high-performance digital circuits can be constructed at high operating frequency, reduced power dissipation, portability, and large density. Using conventional complementary-metal-oxide-semiconductor (CMOS) design process, it is quite difficult to achieve ultra-high-speed circuits due to scaling problems. Recently quantum dot cellular automata (QCA) are prosed to develop logic circuits at atomic level. In this paper, we analyzed the performance of QCA circuits under different temperature effects and observed that polarization of the cells is highly sensitive to temperature. In case of the 3-input majority gate the cell polarization drops to 50% with an increase in the temperature of 18 K and for 5 input majority gate the cell polarization drops more quickly than the 3-input majority. Further, the performance of majority gates also compared in terms of area and power dissipation. It has been noticed that the proposed logic gates can also be used for developing simple and complex and memory circuits

Exploration of Majority Logic Based Designs for Arithmetic Circuits

Since its inception, Moore\u27s Law has been a reliable predictor of computational power. This steady increase in computational power has been due to the ability to fit increasing numbers of transistors in a single chip. A consequence of increasing the number of transistors is also increasing the power consumption. The physical properties of CMOS technologies will make this powerwall unavoidable and will result in severe restrictions to future progress and applications. A potential solution to the problem of rising power demands is to investigate alternative low power nanotechnologies for implementing logic circuits. The intrinsic properties of these emerging nanotechnologies result in them being low power in nature when compared to current CMOS technologies. This thesis specifically highlights quantum dot celluar automata (QCA) and nanomagnetic logic (NML) as just two possible technologies. Designs in NML and QCA are explored for simple arithmetic units such as full adders and subtractors. A new multilayer 5-input majority gate design is proposed for use in NML. Designs of reversible adders are proposed which are easily testable for unidirectional stuck at faults

Emerging Design Methodology And Its Implementation Through Rns And Qca

Digital logic technology has been changing dramatically from integrated circuits, to a Very Large Scale Integrated circuits (VLSI) and to a nanotechnology logic circuits. Research focused on increasing the speed and reducing the size of the circuit design. Residue Number System (RNS) architecture has ability to support high speed concurrent arithmetic applications. To reduce the size, Quantum-Dot Cellular Automata (QCA) has become one of the new nanotechnology research field and has received a lot of attention within the engineering community due to its small size and ultralow power. In the last decade, residue number system has received increased attention due to its ability to support high speed concurrent arithmetic applications such as Fast Fourier Transform (FFT), image processing and digital filters utilizing the efficiencies of RNS arithmetic in addition and multiplication. In spite of its effectiveness, RNS has remained more an academic challenge and has very little impact in practical applications due to the complexity involved in the conversion process, magnitude comparison, overflow detection, sign detection, parity detection, scaling and division. The advancements in very large scale integration technology and demand for parallelism computation have enabled researchers to consider RNS as an alternative approach to high speed concurrent arithmetic. Novel parallel - prefix structure binary to residue number system conversion method and RNS novel scaling method are presented in this thesis. Quantum-dot cellular automata has become one of the new nanotechnology research field and has received a lot of attention within engineering community due to its extremely small feature size and ultralow power consumption compared to COMS technology. Novel methodology for generating QCA Boolean circuits from multi-output Boolean circuits is presented. Our methodology takes as its input a Boolean circuit, generates simplified XOR-AND equivalent circuit and output an equivalent majority gate circuits. During the past decade, quantum-dot cellular automata showed the ability to implement both combinational and sequential logic devices. Unlike conventional Boolean AND-OR-NOT based circuits, the fundamental logical device in QCA Boolean networks is majority gate. With combining these QCA gates with NOT gates any combinational or sequential logical device can be constructed from QCA cells. We present an implementation of generalized pipeline cellular array using quantum-dot cellular automata cells. The proposed QCA pipeline array can perform all basic operations such as multiplication, division, squaring and square rooting. The different mode of operations are controlled by a single control line

Optimized Reversible Logic Multiplexer Designs for Energy-Efficient Nanoscale Computing

Nano- and quantum-based low-power applications are where reversible logic really shines. By using digitally equivalent circuits with reversible logic gates, energy savings may be achieved. Reducing garbage output and ancilla inputs is a primary emphasis of this study, which aims to lower power consumption in reversible multiplexers. Multiplexers with switchable 2:1, 4:1, and 8:1 ratios may be built using the SJ gate and other simple reversible logic gates. The number of ancilla inputs has been cut in half from four to zero, and the amount of garbage output has been cut in half as well, from eight to three, making the 2:1 multiplexer an improvement over the prior design. New 4:1 multiplexer has 10' ancilla inputs, up from 2' in the previous designs. The proposed 4:1 multiplexer also cuts waste production in half from the current 5-to-6 bins per day. The 8:1 multiplexer has two ancilla inputs and nine trash outputs, while the current architecture only has one of each. The functionality of the VHDL and Xilinx 14.7-coded designs is validated by ISIM simulations

Explorations for Efficient Reversible Barrel Shifters and Their Mappings in QCA Nanocomputing

This thesis is based on promising computing paradigm of reversible logic which generates unique outputs out of the inputs and. Reversible logic circuits maintain one-to-one mapping inside of the inputs and the outputs. Compared to the traditional irreversible computation, reversible logic circuit has the advantage that it successfully avoids the information loss during computations. Also, reversible logic is useful to design ultra-low-power nanocomputing circuits, circuits for quantum computing, and the nanocircuits that are testable in nature. Reversible computing circuits require the ancilla inputs and the garbage outputs. Ancilla input is the constant input in reversible circuits. Garbage output is the output for maintaining the reversibility of the reversible logic but is not any of the primary inputs nor a useful bit. An efficient reversible circuit will have the minimal number of garbage and ancilla bits. Barrel shifter is one of main computing systems having applications in high speed digital signal processing, oating-point arithmetic, FPGA, and Center Processing Unit (CPU). It can operate the function of shifting or rotation for multiple bits in only one clock cycle. The goal of this thesis is to design barrel shifters based on the reversible computing that are optimized in terms of the number of ancilla and garbage bits. In order to achieve this goal, a new Super Conservative Reversible Logic Gate (SCRL gate) has been used. The SCRL gate has 1 control input depending on the value of which it can swap any two n-1 data inputs. We proved that the SCRL gate is superior to the existing conservative reversible Fredkin gate. This thesis develops 5 design methodologies for reversible barrel shifters using SCRL gates that are primarily optimized with the criteria of the number of ancilla and garbage bits. The five proposed methodologies consist of reversible right rotator, reversible logical right shifter, reversible arithmetic right shifter, reversible universal right shifter and reversible universal bidirectional shifter. The proposed reversible barrel shifter design is compared with the existing works in literature and have shown improvement ranging from 8.5% to 92% by the number of garbage and ancilla bits. The SCRL gate and design methodologies of reversible barrel shifter are mapped in Quantum Dot Cellular Automata (QCA) computing. It is illustrated that the SCRL-based designs of reversible barrel shifters have less QCA cost (cost in terms of number of inverters and majority voters) compared to the Fredkin gate- based designs of reversible barrel shifters

Security Analysis With Novel Image Masking Based Quantum-Dot Cellular Automata Information Security Model

Mask of an image is generated in this article using Quantum Dot Cellular Automata. An encoder circuit is drafted to produce the Mask Image. This encoder can function as a decoder as well. A mask image is used to retrieve the original image,although the secret key remains unknown. Power dissipation calculations are performed to comprehend the proposed circuit consumes lower power dissipation at nano-scale level design.The security of the proposed circuit is guaranteed by validating with different security standards. The design paradigm matches the theoretical values, which authorizes the accurateness of the proposed circuit. The Structural Similarity (SSIM) index of the retrieved image is calculated to establish the degradation of the image quality is minimal. The stuck-at-fault analysis is performed to prove the stability of the circuit