HETEROGENEOUS GPU&CPU CLUSTER FOR HIGH PERFORMANCE COMPUTING IN CRYPTOGRAPHY

This paper addresses issues associated with distributed computing systems andthe application of mixed GPU&CPU technology to data encryption and decryptionalgorithms. We describe a heterogenous cluster HGCC formed by twotypes of nodes: Intel processor with NVIDIA graphics processing unit and AMDprocessor with AMD graphics processing unit (formerly ATI), and a novel softwareframework that hides the heterogeneity of our cluster and provides toolsfor solving complex scientific and engineering problems. Finally, we present theresults of numerical experiments. The considered case study is concerned withparallel implementations of selected cryptanalysis algorithms. The main goal ofthe paper is to show the wide applicability of the GPU&CPU technology tolarge scale computation and data processing

Implementation of the AES encryption algorithm in parallel cpu and gpu architectures

Το αντικείμενο της παρούσας πτυχιακής εργασίας είναι η υλοποίηση του αλγορίθμου κρυπτογράφησης AES με χρήση CUDA παράλληλου κώδικα, με κύριο στόχο την επίτευξη σημαντικής επιτάχυνσης του αλγορίθμου, σε σχέση με την σειριακή υλοποίησή του. Για την υλοποίηση του λογισμικού, χρησιμοποιήθηκε ο αντίστοιχος κώδικας σε C ως βάση, αν και ενσωματώθηκαν αρκετές αλλαγές, παρ’όλη την συνάφεια που παρουσιάζει η C με την CUDA ως γλώσσες προγραμματισμού. Στην αρχή της ανάπτυξης του κώδικα, καλούμασταν να βρούμε έναν τρόπο να χρησιμοποιήσουμε την CUDA για να παράγουμε ένα πρόγραμμα το οποίο θα είχε ακριβώς την ίδια λειτουργικότητα με τον αρχικό σειριακό. Παρ’ότι αυτό μπορεί να φαίνεται απλό λόγω της ομοιότητας της C με την CUDA, το πραγματικό ζήτημα ήταν να βρούμε έναν τρόπο ώστε να αξιοποιήσουμε όσο δυνατόν καλύτερα το πλήθος των CUDA threads έτσι ώστε να πετύχουμε την καλύτερη δυνατή επιτάχυνση, χωρίς όμως παράλληλα να θυσιαστούν οποιεσδήποτε λειτουργίες του λογισμικού ή να μειωθεί η λειτουργικότητά του. Μετά την ανάπτυξη του CUDA κώδικα, συμπεριλήφθησαν κάποιες διορθώσεις και βελτιστοποιήσεις στο πρόγραμμά μας, έτσι ώστε να μειωθούν κατά το δυνατό οι περιττές και χρονοβόρες διαδικασίες. Στη συνέχεια, συμπεριλάβαμε κάποια εκτελέσιμα tests με σκοπό να μετρήσουμε στην πράξη την επιτάχυνση σε έναν επαναλαμβανόμενο κύκλο Κρυπτογράφισης-Αποκρυπτογράφισης. Τα αποτελέσματα επαλήθευσαν τις αρχικές μας εκτιμήσεις. Τέλος, καταλήξαμε ότι ορισμένες μορφές του AES αλγορίθμου μπορούν να επιταχυνθούν σε σημαντικό βαθμό, έτσι ώστε να ολοκληρώνονται ακόμα και 70 φορές πιο γρήγορα απ’τον σειριακό C κώδικα.The subject of this thesis is the implementation of the AES encryption algorithm in CUDA parallel code, aiming a significant acceleration over the original serial (C language) code. Parallel software development was realized using a baseline serial C code for the AES algorithm, though many changes have taken place, in spite of the similarity of the two implementations. In the beginning of the thesis, we were called to find a way to write code which would have identical functionality to the C code used as a baseline. Though the initial code was in C and CUDA supports C and C++ code, which is something that would make the production of new code seem easy, the main problem was finding a way to make proper use of all available CUDA threads and obtain the best possible acceleration, without removing any features of the algorithm or reducing its functionality. After the finalization and validation of the CUDA code, we implemented performance optimizations. Finally we developed some tests to determine the actual (real-time, not theoretical) acceleration to an Encryption-Decryption procedure, performed several (10/100/1000) times. Results confirmed our intuition. In conclusion, certain variants of the AES encryption algorithm can be accelerated by GPUs obtaining significantly improved performance, which could reach acceleration levels up to 70 times compared to the baseline serial code

Hardware accelerated authentication system for dynamic time-critical networks

The secure and efficient operation of time-critical networks, such as vehicular networks, smart-grid and other smart-infrastructures, is of primary importance in today’s society. It is crucial to minimize the impact of security mechanisms over such networks so that the safe and reliable operations of time-critical systems are not being interfered. Even though there are several security mechanisms, their application to smart-infrastructure and Internet of Things (IoT) deployments may not meet the ubiquitous and time-sensitive needs of these systems. That is, existing security mechanisms either introduce a significant computation and communication overhead, or they are not scalable for a large number of IoT components. In particular, as a primary authentication mechanism, existing digital signatures cannot meet the real-time processing requirements of time-critical networks, and also do not fully benefit from advancements in the underlying hardware/software of IoTs. As a part of this thesis, we create a reliable and scalable authentication system to ensure secure and reliable operation of dynamic time-critical networks like vehicular networks through hardware acceleration. The system is implemented on System-On-Chips (SoC) leveraging the parallel processing capabilities of the embedded Graphical Processing Units (GPUs) along with the CPUs (Central Processing Units). We identify a set of cryptographic authentication mechanisms, which consist of operations that are highly parallelizable while still maintain high standards of security and are also secure against various malicious adversaries. We also focus on creating a fully functional prototype of the system which we call a “Dynamic Scheduler” which will take care of scheduling the messages for signing or verification on the basis of their priority level and the number of messages currently in the system, so as to derive maximum throughput or minimum latency from the system, whatever the requirement may be

The Proceedings of 14th Australian Information Security Management Conference, 5-6 December 2016, Edith Cowan University, Perth, Australia

The annual Security Congress, run by the Security Research Institute at Edith Cowan University, includes the Australian Information Security and Management Conference. Now in its fourteenth year, the conference remains popular for its diverse content and mixture of technical research and discussion papers. The area of information security and management continues to be varied, as is reflected by the wide variety of subject matter covered by the papers this year. The conference has drawn interest and papers from within Australia and internationally. All submitted papers were subject to a double blind peer review process. Fifteen papers were submitted from Australia and overseas, of which ten were accepted for final presentation and publication. We wish to thank the reviewers for kindly volunteering their time and expertise in support of this event. We would also like to thank the conference committee who have organised yet another successful congress. Events such as this are impossible without the tireless efforts of such people in reviewing and editing the conference papers, and assisting with the planning, organisation and execution of the conferences. To our sponsors also a vote of thanks for both the financial and moral support provided to the conference. Finally, thank you to the administrative and technical staff, and students of the ECU Security Research Institute for their contributions to the running of the conference

Journal of Telecommunications and Information Technology, 2017, nr 1

kwartalni

Journal of Telecommunications and Information Technology, 2012, nr 3

kwartalni

Parallel cryptanalysis

Most of today’s cryptographic primitives are based on computations that are hard to perform for a potential attacker but easy to perform for somebody who is in possession of some secret information, the key, that opens a back door in these hard computations and allows them to be solved in a small amount of time. To estimate the strength of a cryptographic primitive it is important to know how hard it is to perform the computation without knowledge of the secret back door and to get an understanding of how much money or time the attacker has to spend. Usually a cryptographic primitive allows the cryptographer to choose parameters that make an attack harder at the cost of making the computations using the secret key harder as well. Therefore designing a cryptographic primitive imposes the dilemma of choosing the parameters strong enough to resist an attack up to a certain cost while choosing them small enough to allow usage of the primitive in the real world, e.g. on small computing devices like smart phones. This thesis investigates three different attacks on particular cryptographic systems: Wagner’s generalized birthday attack is applied to the compression function of the hash function FSB. Pollard’s rho algorithm is used for attacking Certicom’s ECC Challenge ECC2K-130. The implementation of the XL algorithm has not been specialized for an attack on a specific cryptographic primitive but can be used for attacking some cryptographic primitives by solving multivariate quadratic systems. All three attacks are general attacks, i.e. they apply to various cryptographic systems; the implementations of Wagner’s generalized birthday attack and Pollard’s rho algorithm can be adapted for attacking other primitives than those given in this thesis. The three attacks have been implemented on different parallel architectures. XL has been parallelized using the Block Wiedemann algorithm on a NUMA system using OpenMP and on an Infiniband cluster using MPI. Wagner’s attack was performed on a distributed system of 8 multi-core nodes connected by an Ethernet network. The work on Pollard’s Rho algorithm is part of a large research collaboration with several research groups; the computations are embarrassingly parallel and are executed in a distributed fashion in several facilities with almost negligible communication cost. This dissertation presents implementations of the iteration function of Pollard’s Rho algorithm on Graphics Processing Units and on the Cell Broadband Engine