A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording

Bistability and Electrical Characterisation of Two Terminal Non-Volatile Polymer Memory Devices.

Polymer blended with nanoparticle and ferroelectric materials in two terminal memory devices has potential for electronic memory devices that may offer increased storage capacity and performance. Towards understanding the memory performance of a combination of an organic polymer with a ferroelectric or unpolarised material, this research is concerned with testing the memory programming and capacitance of these materials using two-terminal memory device structures. This research contributes to previous investigation into the internal working mechanisms of polymer memory devices and increases understanding and verifies the principles of these mechanisms through testing previously untested materials in different material compositions. This study makes a novel contribution by testing the electrical bistability of new materials; specifically, nickel oxide, barium titanate and methylammonium lead bromide and considers their properties which include nanoparticles, ferroelectric, perovskite structures and organic-inorganic composition. Due to their material properties which have different implications for internal switching and memory storage. Nanoparticles have a greater band gap between the valence band and conduction band compare to bulk material which is exploited for memory storage and ferroelectric properties and perovskite materials have non-volatile properties suitable for switching mechanisms. Specific attributes of memory function which include charging mechanism, device programming, capacitance and charge retention were tested for different material compositions which included, blend and layered with a PVAc polymer, and as a bulk material with a single crystal structure using MIM memory devices and MIS device structures. The results showed that nickel oxide was the most effective material as a blend with the polymer for memory performance, this was followed by barium titanate, however, methylammonium lead bromide performed poorly with polymer but showed promise as a single crystal structure. The results also showed that an increase in concentration of the tested material in a blend composition resulted in a corresponding increase in memory function, and that blend compositions were much more effective than layered compositions

Charge-based compact model of gate-all-around floating gate nanowire with variable oxide thickness for flash memory cell

Due to high gate electrostatic control and introduction of punch and plug process technology, the gate-all-around (GAA) transistor is very promising in, and apparently has been utilized for, flash memory applications. However, GAA Floating Gate (GAA-FG) memory cell still requires high programming voltage that may be susceptible to cell-to-cell interference. Scaling down the tunnel oxide can reduce the Program/Erase (P/E) voltage but degrades the data retention capability. By using Technology-Computer-Aided-Design (TCAD) tools, the concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack is utilized in compensating the trade-off between P/E operation and retention characteristics. Four high-k dielectrics (Si3N4, Al2O3, HfO2 and ZrO2) that are commonly used in semiconductor process technology are examined with SiO2 as its low-k dielectric. It is found that by using SiO2/Al2O3 as the tunnel layer, both the P/E and retention characteristics of GAA-FG can be compensated. About 30% improvement in memory window than conventional SiO2 is obtained and only 1% of charge-loss is predicted after 10 years of applying gate stress of -3.6V. Compact model of GAA-FG is initiated by developing a continuous explicit core model of GAA transistor (GAA Nanowire MOSFET (GAANWFET) and Juntionless Nanowire Transitor (JNT)). The validity of the theory and compact model is identified based on sophisticated numerical TCAD simulator for under 10% maximum error of surface potential. It is revealed that with the inclusion of partial-depletion conduction, the accuracy of the core model for GAANWFET is improved by more than 50% in the subthreshold region with doping-geometry ratio can be as high as about 0.86. As for JNT, despite the model being accurate for doping-geometry ratio upto 0.6, it is also independent of fitting parameters that may vary under different terminal biases or doping-geometry cases. The compact model of GAA-FG is completed by incorperating Charge Balance Model (CBM) into GAA transistor core model where good agreement is obtained with TCAD simulation and published experimental work. The CBM gives better accuracy than the conventional capacitive coupling approach under subthreshold region with approximately 10% error of floating gate potential. Therefore, the proposed compact model can be used to assist experimental work in extracting experimental data