A Discrete-Time Technique for Linearity Enhancement of Wideband Receivers

A new signal processing technique is introduced to enhance the linearity performance of wideband radio frequency (RF) receivers. The proposed technique combines the advancements in mixer first architectures with a library of binary sequences as local oscillator signals to enable wide instantaneous bandwidth and high linearity for the RF receiver. To do so, N-bit pseudo-random-binary-sequences (PRBS) are used as local oscillator signals. The RF input signal is multiplied with the PRBS at the mixer and then averaged over the full sequence. This in effect reduces the amplitude of the signal and improves the overall linearity of the system. In order to enable full reconstruction of the input signal N channels are used with each employing a shifted version of a PRBS. The effect of the proposed technique on different aspects of the system performance such as noise and linearity is discussed. In addition, the effect of nonidealities stemming from hardware implementation on the overall performance are studied. A prototype integrated circuit (IC) is implemented in 130\,nm CMOS technology to demonstrate the feasibility of the proposed technique. The design procedure of each circuit block is described and simulation results are used to evaluate the performance. The device is fabricated and characterized using a custom data acquisition system. Measurement results show good agreement with the expected values from simulation and analytical analysis. Calibration techniques are introduced to minimize the effect of DC offsets, gain mismatches, and timing skews. Modifications to the implemented CMOS circuit are proposed to enable such calibrations and further enhance the overall performance of the system. The requirements for the precision of calibration techniques are derived and used to find the specifications of circuit block that are designed to enable these techniques. Calibration of DC offsets along with gain mismatches is carried out for the fabricated IC and results are shown. A digitally assisted technique is proposed to enable the calibration of timing skews. In addition, a review of additional implementation shortcomings that can affect the system performance are reviewed. Finally, a conclusion of the dissertation is presented along with potential future work for further enhancement of the system performance

High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems

abstract: Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Direct sampling receivers for broadband communications

Today everything tends to be connected in the Internet of Things (IoT) universe, where a broad variety of communication standards and technologies are used for those connected devices. It is always a dream to design a Software-Defined Radio (SDR) supporting different standards solely based on the software configuration. As integrated-circuit (IC) manufacture and design advance, a partial of SDR can be realized. This thesis investigates one of the most important parts in a SDR: the analog design of a direct sampling (DS) receiver, which mainly consists of a broadband RF front end and a wideband ADC. Especially, a DS receiver shows a great flexibility and efficiency for the simultaneous reception of multiple channels comparing with the traditional parallelism of superheterodyne structure. The research contributions of this work include (1) demonstration and comparative analysis of two new architectures of broadband RFPGAs: voltage-mode: RFPGA-V and current-mode: RFPGA-I. RFPGA-V and RFPGA-I utilize an innovative interpolation method and current steering approach, respectively, to achieve a fine gain step of 0.25-dB over 40-dB gain range for several GHz frequency range. Besides, with innovative design, no off-chip inductor is needed for the both RFPGAs. (2) The design of a 5-GS/s 10b time-interleaved SAR. The ADC power efficiency is significantly improved by many design techniques: the low-energy CDAC switching scheme, optimized input common-mode voltage for comparator, optimal reduced radix-2 capacitor ratio for low-power reference buffers and higher conversion speed, etc. The lane-to-lane mismatches in a time-interleave ADC are minimized by using optimal floor plan and then are calibrated digitally. Three prototypes: the broadband RF front ends with RFPGA-V, the broadband RF front ends with RFPGA-I and a 5-GHz ADC, are fabricated to verify the proposed ideas in 28nm CMOS technology.Electrical and Computer Engineerin

Etude et conception d'algorithmes de correction d'erreurs dans des structures de conversion analogique-numérique entrelacées pour applications radar et guerre électronique

The evolution of radar and electronic warfare systems tends to develop digitalreceivers with wider bandwidths. This constraint reaches the Analog to Digital Converters(ADC) which must provide a sample rate higher and higher while maintaining a reducedpower dissipation. A solution to meet this demand is the Time-Interleaved ADC (TIADC)which parallelizes M ADCs, increasing the sampling frequency of an M factor while still ina proportionate relation to the power loss. However, the dynamic performance of TIADCsare reduced by errors related to the mismatches between the sampling channels, due to themanufacturing processes, the supply voltage and the temperature variations. These errors canbe modeled as the result of offset, gain and clock-skew mismatches and globally as from thefrequency response mismatches. It is these last mismatches, unless addressed in the literaturethat carry our work. The objective is to study these errors to derive a model and an estimationmethod then, to propose digital compensation methods that can be implemented on a FPGAtarget.First, we propose a general TIADC model using frequency response mismatches for any Mchannel number. Our model merge a continuous-time description of mismatches and a discretetimeone of the interleaving process, resulting in an expression of the TIADC errors as a linearperiodic time-varying (LPTV) system applied to the uniformly sampled analog signal. Then,we propose a method to estimate TIADC errors based on the correlation properties of theoutput signal for any M channel. Next, we define a frequency response mismatch compensationarchitecture for TIADC errors and we study its performance related to its configuration and theinput signal. We describe an FPGA implementation of this architecture for M=4 interleavedchannels and we study the resources consumption to propose optimisations. Finally, we proposea second compensation method, specific to M=2 interleaved channels and derived from the firstone, but working on the analytical signal from the TIADC output and we compare it to a similarstate-of-the-art method.L’ évolution des systèmes radar et de guerre électronique tend à concevoir desrécepteurs numériques possédant des bandes instantanées de plus en plus larges. Cette contraintese reporte sur les Convertisseurs Analogique-Numérique (CAN) qui doivent fournir une fréquenced’échantillonnage de plus en plus élevée tout en conservant une puissance dissipée réduite. Unesolution pour répondre à cette demande est le CAN à Temps Entrelacés (ET-CAN) qui paralléliseM CANs pour augmenter la fréquence d’échantillonnage d’un facteur M tout en restant dansun rapport proportionné avec la puissance dissipée. Cependant, les performances dynamiquesdes ET-CANs sont réduites par des défauts d’entrelacements liés à des différences de processusde fabrication, de leur tension d’alimentation et des variations de température. Ces défautspeuvent être modélisés comme issus des disparités d’offsets, de gains ou décalages temporels etglobalement comme issus des disparités de réponses fréquentielles. Ce sont sur ces dernièresdisparités, moins traitées dans la littérature, que portent nos travaux. L’objectif est d’étudierces disparités pour en déduire un modèle et une méthode d’estimation puis, de proposer desméthodes de compensation numérique qui peuvent être implémentées sur une cible FPGA.Pour cela, nous proposons un modèle général des disparités de réponses fréquentielles desET-CANs pour un nombre de voies M quelconques. Celui-ci mélange une description continuedes disparités et une description discrète de l’entrelacement, résultant sur une expression desdéfauts des ET-CANs comme un filtrage à temps variant périodique (LPTV) du signal analogiqueéchantillonné uniformément. Puis, nous proposons une méthode d’estimation des disparitésdes ET-CANs basée sur les propriétés de corrélation du signal en sortie du modèle, pour Mvoies quelconques. Ensuite, nous définissions une architecture de compensation des disparitésde réponses fréquentielles des ET-CANs et nous étudions ses performances en fonction de sesconfigurations et du signal en entrée. Nous décrivons une implémentation de cette architecturepour M=4 voies entrelacées sur cible FPGA et nous étudions les ressources consommées afin deproposer des pistes d’optimisation. Enfin, nous proposons une seconde méthode de compensationspécifique au cas M=2 voies entrelacées, dérivée de la première mais travaillant sur le signalanalytique en sortie d’un ET-CAN et nous la comparons à une méthode similaire de l’état del’art