A survey on continuous-time modulators : theory, designs and implementations

Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay. In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.Keywords: Continuous-Time, Delta-Sigm

Entwurfsregeln für supraleitende Analog-Digital-Wandler

This Thesis is a contribution for dimensioning aspects of circuits designs in superconductor electronics. Mainly superconductor comparators inclusive Josephson comparators as well as QOJS-Comparators are investigated. Both types were investigated in terms of speed and sensitivity. The influence of the thermal noise on the decision process of the comparators represent in so called gray zone, which is analysed in this thesis. Thereby, different relations between design parameters were derived. A circuit model of the Josephson comparator was verified by experiments. Concepts of superconductor analog-to-digital converters, which are based on above called comparators, were investigated in detail. From the comparator design rules, new rules for AD-converters were derived. Because of the reduced switching energy, the signal to noise ratio (SNR) of the circuits is affected and therefore the reliability of the decision-process is affected. For special applications with very demanding requirements in terms of the speed and accuracy superconductor analog-to-digital converters offer an excellent performance. This thesis provides relations between different design paramenters and shows resulting trade-offs, This method is transparent and easy to transfer to other circuit topologies. As a main result, a highly predictive tool for dimensioning of superconducing ADC's is proved.Die vorliegende Dissertationsschrift liefert einen Beitrag zu Dimensionierungsaspekten des Schaltungsentwurfs in der supraleitender Elektronik. Dazu werden supraleitende Komparatoren, d. h. Josephson-Komparator und QOJS-Komparator bezüglich der Geschwindigkeit und der Empfindlichkeit untersucht. Der Einfluss des thermischen Rauschens auf den Entscheidungsprozess der Komparatoren repräsentiert die so genannte Grauzone. Sie wird in der Arbeit als wichtige Kennzahl ausführlich analysiert. Daraus werden verschiedene Parameterabhängigkeiten dargestellt. Eine Modellierung eines Josephson-Komparator wurde experimentell bestätigt. Darauf aufbauend werden Konzepte von supraleitenden Analog-Digital-Wandlern in der Arbeit untersucht und daraus Entwurfsregeln abgeleitet. Durch die Reduzierung der Schaltenegie wird das Signal-Rausch-Verhältnis (SNR) der Schaltungen und damit die Zuverlässigkeit von Entscheidungsprozessen und Schaltvorgängen beeinflusst. Für Spezialanwendungen mit sehr hohen Anforderungen bezüglich der Geschwindigkeit oder Genauigkeit bieten supraleitende AD-Wandler ausgezeichnete Leistungsmerkmale an. Die Arbeit liefert konkrete Zusammenhänge zwischen den unterschiedlichen Entwurfsparametern und zeigt mögliche Kompromisse auf. Die Methoden sind transparent dargestellt und lassen sich leicht auf andere Schaltungstopologien übertragen. Im Ergebnis wird ein Werkzeug zur objektiven Dimensionierung von supraleitenden AD-Wandlern bereitgestellt

Low-voltage low-power continuous-time delta-sigma modulator designs

Ph.DDOCTOR OF PHILOSOPH

Analysis of Current Conveyor based Switched Capacitor Circuits for Application in ∆Σ Modulators

The reduction in supply voltage, loss of dynamic range and increased noise prevent the analog circuits from taking advantage of advanced technologies. Therefore the trend is to move all signal processing tasks to digital domain where advantages of technology scaling can be used. Due to this, there exists a need for data converters with large signal bandwidths, higher speeds and greater dynamic range to act as an interface between real world analog and digital signals. The Delta Sigma (∆Σ) modulator is a data converter that makes use of large sampling rates and noise shaping techniques to achieve high resolution in the band of interest. The modulator consists of analog integrators and comparators which create a modulated digital bit stream whose average represents the input value. Due to their simplicity, they are popular in narrow band receivers, medical and sensor applications. However Operational Amplifiers (Op-Amps) or Operational Transconductance Amplifiers (OTAs), which are commonly used in data converters, present a bottleneck. Due to low supply voltages, designers rely on folded cascode, multistage cascade and bulk driven topologies for their designs. Although the two stage or multistage cascade topologies offer good gain and bandwidth, they suffer from stability problems due to multiple stages and feedback requiring large compensation capacitors. Therefore other low voltage Switched-Capacitor (SC) circuit techniques were developed to overcome these problems, based on inverters, comparators and unity gain buffers. In this thesis we present an alternative approach to design of ∆Σ modulators using Second Generation Current Conveyors (CCIIs). The important feature of these modulators is the replacement of the traditional Op-Amp based SC integrators with CCII based SC integrators. The main design issues such as the effect of the non-idealities in the CCIIs are considered in the operation of SC circuits and solutions are proposed to cancel them. Design tradeoffs and guidelines for various components of the circuit are presented through analysis of existing and the proposed SC circuits. A two step adaptive calibration technique is presented which uses few additional components to measure the integrator input output characteristic and linearize it for providing optimum performance over a wide range of sampling frequencies while maintaining low power and area. The presented CCII integrator and calibration circuit are used in the design of a 4th order (2-2 cascade) ∆Σ modulator which has been fabricated in UMC 90nm/1V technology through Europractice. Experimental values for Signal to Noise+Distortion Ratio (SNDR), Dynamic Range (DR) and Figure Of Merit (FOM) show that the modulator can compete with state of art reconfigurable Discrete-Time (DT) architectures while using lower gain stages and less design complexity