231 research outputs found
A Survey of Asynchronous Programming Using Coroutines in the Internet of Things and Embedded Systems
Many Internet of Things and embedded projects are event-driven, and therefore
require asynchronous and concurrent programming. Current proposals for C++20
suggest that coroutines will have native language support. It is timely to
survey the current use of coroutines in embedded systems development. This
paper investigates existing research which uses or describes coroutines on
resource-constrained platforms. The existing research is analysed with regard
to: software platform, hardware platform and capacity; use cases and intended
benefits; and the application programming interface design used for coroutines.
A systematic mapping study was performed, to select studies published between
2007 and 2018 which contained original research into the application of
coroutines on resource-constrained platforms. An initial set of 566 candidate
papers were reduced to only 35 after filters were applied, revealing the
following taxonomy. The C & C++ programming languages were used by 22 studies
out of 35. As regards hardware, 16 studies used 8- or 16-bit processors while
13 used 32-bit processors. The four most common use cases were concurrency (17
papers), network communication (15), sensor readings (9) and data flow (7). The
leading intended benefits were code style and simplicity (12 papers),
scheduling (9) and efficiency (8). A wide variety of techniques have been used
to implement coroutines, including native macros, additional tool chain steps,
new language features and non-portable assembly language. We conclude that
there is widespread demand for coroutines on resource-constrained devices. Our
findings suggest that there is significant demand for a formalised, stable,
well-supported implementation of coroutines in C++, designed with consideration
of the special needs of resource-constrained devices, and further that such an
implementation would bring benefits specific to such devices.Comment: 22 pages, 8 figures, to be published in ACM Transactions on Embedded
Computing Systems (TECS
A low-cost implementation of coroutines for C
We identify a set of primitive operations supporting coroutines, and demonstrate their usefulness. We then address their implementation in C according to a set of criteria aimed at maintaining simplicity, and achieve a satisfactory compromise between it and effectiveness. Our package for the PDP-II under UNIX allows users of coroutines in C programs to gain access to the primitives via an included definitions file and an object library; no penalty is imposed upon non-coroutine users
DOWNBEAT : Development of an adaptive combat system based on the use of the downbeats and upbeats of a musical piece
Treball final de Grau en Disseny i Desenvolupament de Videojocs. Codi: VJ1241. Curs acadĂšmic: 2019/2020This document presents the Final Report of a Bachelorâs Thesis in the Degree in Video Game
Design and Development.
The project consists of the composition, production, implementation and analysis of a dynamically
changing musical piece and the development of a playable demonstration of a unique, challenging
and innovative combat system based on three main concepts: rhythm , strategy and reactivity .
This combat system is oriented to boss fights and proposes a symbiotic relationship between
music, visuals, narrative and mechanics. Therefore, in addition to mainly dealing with aspects
related to the combat demonstration, this document will also cover narrative aspects of DownBeat
âthe complete game to which this combat system would belongâ with the intention of facilitating
the understanding of both the musical and the non-musical narrative background
Game Engines and MAS: BDI & Artifacts in Unity
In questa tesi vedremo un breve sunto riguardo lo stato dei Sistemi Multi-Agente e andremo ad analizzare le limitazioni che attualmente ne impediscono l'utilizzo ai programmatori di videogiochi. Dopodiché, andremo a proporre un nuovo linguaggio BDI, basato su Prolog e inspirato a Jason, che, grazie all'interprete Prolog sviluppato da I. Horswill, darà la possibilità al programmatore di videogiochi di esprimere comportamenti dichiarativi di alto livello per agenti autonomi all'interno del game engine Unity. Andremo anche a proporre una versione di Artefatto per la modellazione dell'ambiente in una scena Unity e un layer di comunicazione che agenti e artefatti possano utilizzare per interagire tra loro. Infine presenteremo un caso di studio per sottolineare i benefici che questo sistema fornisce
Programmiersprachen und Rechenkonzepte
Seit 1984 veranstaltet die GI-Fachgruppe "Programmiersprachen und Rechenkonzepte" regelmĂ€Ăig im FrĂŒhjahr einen Workshop im Physikzentrum Bad Honnef. Das Treffen dient in erster Linie dem gegenseitigen Kennenlernen, dem Erfahrungsaustausch, der Diskussion und der Vertiefung gegenseitiger Kontakte. In diesem Forum werden VortrĂ€ge und Demonstrationen sowohl bereits abgeschlossener als auch noch laufender Arbeiten vorgestellt, unter anderem (aber nicht ausschlieĂlich) zu Themen wie - Sprachen, Sprachparadigmen, - Korrektheit von Entwurf und Implementierung, -Werkzeuge, -Software-/Hardware-Architekturen, -Spezifikation, Entwurf, - Validierung, Verifikation, - Implementierung, Integration, - Sicherheit (Safety und Security), - eingebettete Systeme, - hardware-nahe Programmierung. In diesem Technischen Bericht sind einige der prĂ€sentierten Arbeiten zusammen gestellt
A Formal, Resource Consumption-Preserving Translation of Actors to Haskell
We present a formal translation of an actor-based language with cooperative
scheduling to the functional language Haskell. The translation is proven
correct with respect to a formal semantics of the source language and a
high-level operational semantics of the target, i.e. a subset of Haskell. The
main correctness theorem is expressed in terms of a simulation relation between
the operational semantics of actor programs and their translation. This allows
us to then prove that the resource consumption is preserved over this
translation, as we establish an equivalence of the cost of the original and
Haskell-translated execution traces.Comment: Pre-proceedings paper presented at the 26th International Symposium
on Logic-Based Program Synthesis and Transformation (LOPSTR 2016), Edinburgh,
Scotland UK, 6-8 September 2016 (arXiv:1608.02534
UVM testbench in Python:feature and performance comparison with SystemVerilog implementation
Abstract. Python is emerging as a new language for functional verification of digital integrated circuits (ICs). With the Python verification framework cocotb enabling to write testbenches in Python, new libraries are being developed for various verification techniques and methodologies, such as functional coverage, constrained random verification and Universal Verification Methodology (UVM). Python testbenches have been used in some research and product development, but there is little information available on their performance, and no studies about applying UVM in Python have been published.
In this thesis, a Python UVM testbench was developed using pyuvm and other Python verification libraries for an AHB-Lite slave IP, and a matching testbench in SystemVerilog was also built to examine the differences in their implementations. Testbench codebase sizes, simulation execution times, memory use and coverage accumulation were compared. The Python testbench had 30% less lines of code, suggesting that testbench development may be faster in Python than SystemVerilog. The execution times of the Python testbench on commercial simulators were 8 to 21 times longer than those of the SystemVerilog testbench in tests with AHB-Lite write operations and random stimulus.
In conclusion, given the performance gap and the UVM Register Abstraction Layer (RAL) being at an early stage of development in pyuvm, the studied Python libraries are not competitive with SystemVerilog and its UVM implementation for verifying complex designs like systems-on-chip (SoCs) at this stage. Nevertheless, pyuvm enables Python programmers and users of open-source simulators without support for SystemVerilog UVM to start using the methodology. A Python UVM testbench based on pyuvm is currently viable for verifying simple designs, and it opens new avenues of research in digital IC verification.TiivistelmÀ. Python on nousemassa uudeksi kieleksi digitaalisten integroitujen piirien varmennukseen. Cocotb-viitekehys mahdollistaa testipenkkien kirjoittamisen Pythonilla, ja uusia Python-kirjastoja kehitetÀÀn eri varmennusmenetelmille, kuten funktionaaliselle kattavuudelle, rajoitetulla satunnaisherÀtteellÀ verifioinnille ja universaalille varmennusmenetelmÀlle (engl. Universal Verification Methodology, UVM). Python-testipenkkejÀ on pienissÀ mÀÀrin kÀytetty tutkimuksissa ja tuotekehityksessÀ, mutta niiden suorituskyvystÀ on hyvin vÀhÀn tietoa, ja UVM:n kÀytöstÀ Pythonilla ei ole julkaistu tutkimuksia.
TĂ€ssĂ€ työssĂ€ kehitettiin UVM-testipenkki Pythonilla AHB-Lite-orjana toimivalle IP-lohkolle kĂ€yttĂ€en pyuvm:ÀÀ ja muita Python-verifiointikirjastoja, ja vastaava testipenkki luotiin myös SystemVerilogilla toteutusten vertailua varten. TestipenkeistĂ€ verrattiin koodikannan kokoa, suoritusaikaa, muistin kĂ€yttöÀ ja kattavuuden kertymistĂ€. Python-testipenkissĂ€ oli 30 % vĂ€hemmĂ€n koodirivejĂ€, mikĂ€ voi merkitĂ€, ettĂ€ testipenkkien kehittĂ€minen Pythonilla on nopeampaa kuin SystemVerilogilla. Suoritusajat kaupallisilla simulaattoreilla oli Python-testipenkillĂ€ 8â21 kertaa pidempiĂ€ kuin SystemVerilog-testipenkillĂ€ testeissĂ€, joissa ajettiin AHB-Lite -kirjoitusoperaatioita ja satunnaisherĂ€tettĂ€.
Koska suorituskykyero oli nÀin merkittÀvÀ, ja koska UVM:n rekisteriabstraktiotaso (engl. Register Abstraction Layer, RAL) on vasta alkutekijöissÀÀn pyuvm:ssÀ, voidaan todeta, ettÀ tutkitut Python-kirjastot eivÀt ole vielÀ nykyisellÀ tasollaan kilpailukykyisiÀ SystemVerilogin ja sen UVM-implementaation kanssa monimutkaisten piirien kuten jÀrjestelmÀpiirien varmennukseen. SiitÀ huolimatta pyuvm mahdollistaa UVM:n kÀytön Python-ohjelmoijille ja avoimen lÀhdekoodin simulaattoreissa, joissa ei ole vielÀ SystemVerilog UVM:lle tukea. Pyuvm-pohjainen Python UVM-testipenkki soveltuu tÀllÀ hetkellÀ yksinkertaisten mallien varmennukseen ja avaa uusia tutkimussuuntia digitaalisten integroitujen piirien varmennukseen
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