25 research outputs found

    Performance analysis of multichannel lattice equalization in coherent underwater communications

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    This work examines the numerical fixed-point performance of a new multichannel lattice RLS filtering algorithm using data from two underwater acoustic communication experiments. The algorithm may be an appealing choice for underwater equalization due to its robust numerical behavior and linear scaling of the computational complexity with filter order. Simple modifications to widely-used methods for carrier/timing synchronization and symbol slicing in transversal equalizers are proposed. Experimental results show that the algorithm is as accurate as the similarly array-based QR-RLS, tolerating word lengths as low as 16-20 bits with minor degradation relative to floating-point benchmarks. These features, coupled with a very modular and regular structure, are highly desirable in energyefficient hardware or embedded implementations.FC

    Adaptive Interference Mitigation in GPS Receivers

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    Satellite navigation systems (GNSS) are among the most complex radio-navigation systems, providing positioning, navigation, and timing (PNT) information. A growing number of public sector and commercial applications rely on the GNSS PNT service to support business growth, technical development, and the day-to-day operation of technology and socioeconomic systems. As GNSS signals have inherent limitations, they are highly vulnerable to intentional and unintentional interference. GNSS signals have spectral power densities far below ambient thermal noise. Consequently, GNSS receivers must meet high standards of reliability and integrity to be used within a broad spectrum of applications. GNSS receivers must employ effective interference mitigation techniques to ensure robust, accurate, and reliable PNT service. This research aims to evaluate the effectiveness of the Adaptive Notch Filter (ANF), a precorrelation mitigation technique that can be used to excise Continuous Wave Interference (CWI), hop-frequency and chirp-type interferences from GPS L1 signals. To mitigate unwanted interference, state-of-the-art ANFs typically adjust a single parameter, the notch centre frequency, and zeros are constrained extremely close to unity. Because of this, the notch centre frequency converges slowly to the target frequency. During this slow converge period, interference leaks into the acquisition block, thus sabotaging the operation of the acquisition block. Furthermore, if the CWI continuously hops within the GPS L1 in-band region, the subsequent interference frequency is locked onto after a delay, which means constant interference occurs in the receiver throughout the delay period. This research contributes to the field of interference mitigation at GNSS's receiver end using adaptive signal processing, predominately for GPS. This research can be divided into three stages. I first designed, modelled and developed a Simulink-based GPS L1 signal simulator, providing a homogenous test signal for existing and proposed interference mitigation algorithms. Simulink-based GPS L1 signal simulator provided great flexibility to change various parameters to generate GPS L1 signal under different conditions, e.g. Doppler Shift, code phase delay and amount of propagation degradation. Furthermore, I modelled three acquisition schemes for GPS signals and tested GPS L1 signals acquisition via coherent and non-coherent integration methods. As a next step, I modelled different types of interference signals precisely and implemented and evaluated existing adaptive notch filters in MATLAB in terms of Carrier to Noise Density (\u1d436/\u1d4410), Signal to Noise Ratio (SNR), Peak Degradation Metric, and Mean Square Error (MSE) at the output of the acquisition module in order to create benchmarks. Finally, I designed, developed and implemented a novel algorithm that simultaneously adapts both coefficients in lattice-based ANF. Mathematically, I derived the full-gradient term for the notch's bandwidth parameter adaptation and developed a framework for simultaneously adapting both coefficients of a lattice-based adaptive notch filter. I evaluated the performance of existing and proposed interference mitigation techniques under different types of interference signals. Moreover, I critically analysed different internal signals within the ANF structure in order to develop a new threshold parameter that resets the notch bandwidth at the start of each subsequent interference frequency. As a result, I further reduce the complexity of the structural implementation of lattice-based ANF, allowing for efficient hardware realisation and lower computational costs. It is concluded from extensive simulation results that the proposed fully adaptive lattice-based provides better interference mitigation performance and superior convergence properties to target frequency compared to traditional ANF algorithms. It is demonstrated that by employing the proposed algorithm, a receiver is able to operate with a higher dynamic range of JNR than is possible with existing methods. This research also presents the design and MATLAB implementation of a parameterisable Complex Adaptive Notch Filer (CANF). Present analysis on higher order CANF for detecting and mitigating various types of interference for complex baseband GPS L1 signals. In the end, further research was conducted to suppress interference in the GPS L1 signal by exploiting autocorrelation properties and discarding some portion of the main lobe of the GPS L1 signal. It is shown that by removing 30% spectrum of the main lobe, either from left, right, or centre, the GPS L1 signal is still acquirable

    Digital Filter Design Using Improved Teaching-Learning-Based Optimization

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    Digital filters are an important part of digital signal processing systems. Digital filters are divided into finite impulse response (FIR) digital filters and infinite impulse response (IIR) digital filters according to the length of their impulse responses. An FIR digital filter is easier to implement than an IIR digital filter because of its linear phase and stability properties. In terms of the stability of an IIR digital filter, the poles generated in the denominator are subject to stability constraints. In addition, a digital filter can be categorized as one-dimensional or multi-dimensional digital filters according to the dimensions of the signal to be processed. However, for the design of IIR digital filters, traditional design methods have the disadvantages of easy to fall into a local optimum and slow convergence. The Teaching-Learning-Based optimization (TLBO) algorithm has been proven beneficial in a wide range of engineering applications. To this end, this dissertation focusses on using TLBO and its improved algorithms to design five types of digital filters, which include linear phase FIR digital filters, multiobjective general FIR digital filters, multiobjective IIR digital filters, two-dimensional (2-D) linear phase FIR digital filters, and 2-D nonlinear phase FIR digital filters. Among them, linear phase FIR digital filters, 2-D linear phase FIR digital filters, and 2-D nonlinear phase FIR digital filters use single-objective type of TLBO algorithms to optimize; multiobjective general FIR digital filters use multiobjective non-dominated TLBO (MOTLBO) algorithm to optimize; and multiobjective IIR digital filters use MOTLBO with Euclidean distance to optimize. The design results of the five types of filter designs are compared to those obtained by other state-of-the-art design methods. In this dissertation, two major improvements are proposed to enhance the performance of the standard TLBO algorithm. The first improvement is to apply a gradient-based learning to replace the TLBO learner phase to reduce approximation error(s) and CPU time without sacrificing design accuracy for linear phase FIR digital filter design. The second improvement is to incorporate Manhattan distance to simplify the procedure of the multiobjective non-dominated TLBO (MOTLBO) algorithm for general FIR digital filter design. The design results obtained by the two improvements have demonstrated their efficiency and effectiveness

    An efficient implementation of lattice-ladder multilayer perceptrons in field programmable gate arrays

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    The implementation efficiency of electronic systems is a combination of conflicting requirements, as increasing volumes of computations, accelerating the exchange of data, at the same time increasing energy consumption forcing the researchers not only to optimize the algorithm, but also to quickly implement in a specialized hardware. Therefore in this work, the problem of efficient and straightforward implementation of operating in a real-time electronic intelligent systems on field-programmable gate array (FPGA) is tackled. The object of research is specialized FPGA intellectual property (IP) cores that operate in a real-time. In the thesis the following main aspects of the research object are investigated: implementation criteria and techniques. The aim of the thesis is to optimize the FPGA implementation process of selected class dynamic artificial neural networks. In order to solve stated problem and reach the goal following main tasks of the thesis are formulated: rationalize the selection of a class of Lattice-Ladder Multi-Layer Perceptron (LLMLP) and its electronic intelligent system test-bed – a speaker dependent Lithuanian speech recognizer, to be created and investigated; develop dedicated technique for implementation of LLMLP class on FPGA that is based on specialized efficiency criteria for a circuitry synthesis; develop and experimentally affirm the efficiency of optimized FPGA IP cores used in Lithuanian speech recognizer. The dissertation contains: introduction, four chapters and general conclusions. The first chapter reveals the fundamental knowledge on computer-aideddesign, artificial neural networks and speech recognition implementation on FPGA. In the second chapter the efficiency criteria and technique of LLMLP IP cores implementation are proposed in order to make multi-objective optimization of throughput, LLMLP complexity and resource utilization. The data flow graphs are applied for optimization of LLMLP computations. The optimized neuron processing element is proposed. The IP cores for features extraction and comparison are developed for Lithuanian speech recognizer and analyzed in third chapter. The fourth chapter is devoted for experimental verification of developed numerous LLMLP IP cores. The experiments of isolated word recognition accuracy and speed for different speakers, signal to noise ratios, features extraction and accelerated comparison methods were performed. The main results of the thesis were published in 12 scientific publications: eight of them were printed in peer-reviewed scientific journals, four of them in a Thomson Reuters Web of Science database, four articles – in conference proceedings. The results were presented in 17 scientific conferences

    Implementation of a real time Hough transform using FPGA technology

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    This thesis is concerned with the modelling, design and implementation of efficient architectures for performing the Hough Transform (HT) on mega-pixel resolution real-time images using Field Programmable Gate Array (FPGA) technology. Although the HT has been around for many years and a number of algorithms have been developed it still remains a significant bottleneck in many image processing applications. Even though, the basic idea of the HT is to locate curves in an image that can be parameterized: e.g. straight lines, polynomials or circles, in a suitable parameter space, the research presented in this thesis will focus only on location of straight lines on binary images. The HT algorithm uses an accumulator array (accumulator bins) to detect the existence of a straight line on an image. As the image needs to be binarized, a novel generic synchronization circuit for windowing operations was designed to perform edge detection. An edge detection method of special interest, the canny method, is used and the design and implementation of it in hardware is achieved in this thesis. As each image pixel can be implemented independently, parallel processing can be performed. However, the main disadvantage of the HT is the large storage and computational requirements. This thesis presents new and state-of-the-art hardware implementations for the minimization of the computational cost, using the Hybrid-Logarithmic Number System (Hybrid-LNS) for calculating the HT for fixed bit-width architectures. It is shown that using the Hybrid-LNS the computational cost is minimized, while the precision of the HT algorithm is maintained. Advances in FPGA technology now make it possible to implement functions as the HT in reconfigurable fabrics. Methods for storing large arrays on FPGA’s are presented, where data from a 1024 x 1024 pixel camera at a rate of up to 25 frames per second are processed
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