Automatic recording McLeod gauge Patent

Automatic recording McLeod gage with three electrodes and solenoid valve connectio

Power processor for a 30cm ion thruster

A thermal vacuum power processor for the NASA Lewis 30cm Mercury Ion Engine was designed, fabricated and tested to determine compliance with electrical specifications. The power processor breadboard used the silicon controlled rectifier (SCR) series resonant inverter as the basic power stage to process all the power to an ion engine. The power processor includes a digital interface unit to process all input commands and internal telemetry signals so that operation is compatible with a central computer system. The breadboard was tested in a thermal vacuum environment. Integration tests were performed with the ion engine and demonstrate operational compatibility and reliable operation without any component failures. Electromagnetic interference data were also recorded on the design to provide information on the interaction with total spacecraft

Digital computer control of a 30-cm mercury ion thruster

The major objective was to define the exact role of an onboard spacecraft computer in the control of ion thrusters. An initial computer control system with accurate high speed capability was designed, programmed, and tested with the computer as the sole control element for an operating ion thruster. The command functions and a code format for a spacecraft digital control system were established. A second computer control system was constructed to operate with these functions and format. A throttle program sequence was established and tested. A two thruster array was tested with these computer control systems and the results reported

Minimizing the overheads of dependent {AND}-parallelism

Parallel implementations of programming languages need to control synchronization overheads. Synchronization is essential for ensuring the correctness of parallel code, yet it adds overheads that aren\u27t present in sequential programs. This is an important problem for parallel logic programming systems, because almost every action in such programs requires accessing variables, and the traditional approach of adding synchronization code to all such accesses is so prohibitively expensive that a parallel version of the program may run more slowly on four processors than a sequential version would run on one processor. We present a program transformation for implementing dependent AND-parallelism in logic programming languages that uses mode information to add synchronization code only to the variable accesses that actually need it

Development and flight history of SERT 2 spacecraft

A 25-year historical review of the Space Electric Rocket Test 2 (SERT 2) mission is presented. The Agena launch vehicle; the SERT 2 spacecraft; and mission-peculiar spacecraft hardware, including two ion thruster systems, are described. The 3 1/2-year development period, from 1966 to 1970, that was needed to design, fabricate, and qualify the ion thruster system and the supporting spacecraft components, is documented. Major testing of two ion thruster systems and related auxiliary experiments that were conducted in space after the 3 Feb. 1970, launch are reviewed. Extended ion thruster restarts from 1973 to 1981 are reported, in addition to cross-neutralization tests. Tests of a reflector erosion experiment were continued in 1989 to 1991. The continuing performance of spacecraft subsystems, including the solar arrays, over the 1970-1991 period is summarized. Finally, the knowledge of thruster-spacecraft interactions learned from SERT 2 is listed

Space physics missions handbook

The purpose of this handbook is to provide background data on current, approved, and planned missions, including a summary of the recommended candidate future missions. Topics include the space physics mission plan, operational spacecraft, and details of such approved missions as the Tethered Satellite System, the Solar and Heliospheric Observatory, and the Atmospheric Laboratory for Applications and Science

Optimizing sorting algorithms for the Cell Broadband Engine

The quest for higher performance in computationally intensive tasks is and will always be an ongoing effort. General purpose processors (GPP) have not been sufficient for many of these tasks which has led to research focused towards computing on specialty processors and graphics processing units (GPU). While GPU provide sufficient speedups for some tasks, other specialty processors may be better suited, more economical, or more efficient for different types of tasks. Sorting is an important task in many applications and can be computationally intensive when dealing with large data sets. One such specialty processor that has proven to be a viable solution for sorting is the Cell Broadband Engine (CBE). The CBE is being used as the main platform for this thesis since there are already applications for it that require sorting software. The Cell processor is a general purpose processor that combines one master PowerPC core with eight other vector processors connected via a high bandwidth interconnect bus. The user must explicitly manage the communication, scheduling, and load-balancing between the vector processors and the PowerPC processor to achieve the highest efficiency. By optimizing the sorting algorithms for the vector processors, large speedups can be achieved because multiple operations occur simultaneously. Optimized sorting software is often sought when sorting is not the main purpose of the application. This keeps overheads low so that the performance gains can be realized from the actual code that is to be optimized on specialty processors. Often having sorted datasets enable algorithms to run faster and are more predictably. The motivation behind this thesis is that there is currently no standard library of sorting algorithms that have been optimized for the CBE. Lack of standard libraries makes writing code for the CBE difficult. Results from previous works have also not been sufficient in providing specific measurements of sorting performance. This thesis will explore the development and analysis of a variety of optimized parallel sorting algorithms written for the Cell processor. This thesis will focus on the sorting of both individual elements within vectors as well as sorting entire vectors within arrays. The sorting algorithms, written in C++, that will be optimized and analyzed include, but are not limited to bitonic sort, heap sort, merge sort, and quick sort. A communication management framework will also be created as a main focus of this thesis in order to better understand the architecture of the processor

Peak acceleration limiter for vibrational tester Patent

Electronic detection system for peak acceleration limits in vibrational testing of spacecraft component

Fully automated urban traffic system

The replacement of the driver with an automatic system which could perform the functions of guiding and routing a vehicle with a human's capability of responding to changing traffic demands was discussed. The problem was divided into four technological areas; guidance, routing, computing, and communications. It was determined that the latter three areas being developed independent of any need for fully automated urban traffic. A guidance system that would meet system requirements was not being developed but was technically feasible