Communication Reliability in Network on Chip Designs

The performance of low latency Network on Chip (NoC) architectures, which incorporate fast bypass paths to reduce communication latency, is limited by crosstalk induced skewing of signal transitions on link wires. As a result of crosstalk interactions between wires, signal transitions belonging to the same flit or bit vector arrive at the destination at different times and are likely to violate setup and hold time constraints for the design. This thesis proposes a two-step technique: TransSync- RecSync, to dynamically eliminate packet errors resulting from inter-bit-line transition skew. The proposed approach adds minimally to router complexity and involves no wire overhead. The actual throughput of NoC designs with asynchronous bypass designs is evaluated and the benefits of augmenting such schemes with the proposed design are studied. The TransSync, TransSync-2-lines and RecSync schemes described here are found to improve the average communication latency by 26%, 20% and 38% respectively in a 7X7 mesh NoC with asynchronous bypass channel. This work also evaluates the bit-error ratio (BER) performance of several existing crosstalk avoidance and error correcting schemes and compares them to that of the proposed schemes. Both TransSync and RecSync scheme are dynamic in nature and can be switched on and off on-the-fly. The proposed schemes can therefore be employed to impart unequal error protection (UEP) against intra-flit skewing on NoC links. In the UEP, a larger fraction of the energy budget is spent in providing protection to those parts of the data being transmitted on the link which have a higher priority, while expending smaller effort in protecting relatively less important parts of the data. This allows us to achieve the prescribed level of performance with lower levels of power. The benefits of the presented technique are illustrated using an H.264 video decoder system-on-chip (SoC) employing NoC architecture. We show that for Akyio test streams transmitted over 3mm long link wires, the power consumption can be reduced by as much as 20% at the cost of an acceptable degradation in average peak signal to noise ratio (PSNR) with UEP

Digital System Design - Use of Microcontroller

Embedded systems are today, widely deployed in just about every piece of machinery from toasters to spacecraft. Embedded system designers face many challenges. They are asked to produce increasingly complex systems using the latest technologies, but these technologies are changing faster than ever. They are asked to produce better quality designs with a shorter time-to-market. They are asked to implement increasingly complex functionality but more importantly to satisfy numerous other constraints. To achieve the current goals of design, the designer must be aware with such design constraints and more importantly, the factors that have a direct effect on them.One of the challenges facing embedded system designers is the selection of the optimum processor for the application in hand; single-purpose, general-purpose or application specific. Microcontrollers are one member of the family of the application specific processors.The book concentrates on the use of microcontroller as the embedded system?s processor, and how to use it in many embedded system applications. The book covers both the hardware and software aspects needed to design using microcontroller.The book is ideal for undergraduate students and also the engineers that are working in the field of digital system design.Contents• Preface;• Process design metrics;• A systems approach to digital system design;• Introduction to microcontrollers and microprocessors;• Instructions and Instruction sets;• Machine language and assembly language;• System memory; Timers, counters and watchdog timer;• Interfacing to local devices / peripherals;• Analogue data and the analogue I/O subsystem;• Multiprocessor communications;• Serial Communications and Network-based interfaces

Experimental Evaluation of Growing and Pruning Hyper Basis Function Neural Networks Trained with Extended Information Filter

In this paper we test Extended Information Filter (EIF) for sequential training of Hyper Basis Function Neural Networks with growing and pruning ability (HBF-GP). The HBF neuron allows different scaling of input dimensions to provide better generalization property when dealing with complex nonlinear problems in engineering practice. The main intuition behind HBF is in generalization of Gaussian type of neuron that applies Mahalanobis-like distance as a distance metrics between input training sample and prototype vector. We exploit concept of neuron’s significance and allow growing and pruning of HBF neurons during sequential learning process. From engineer’s perspective, EIF is attractive for training of neural networks because it allows a designer to have scarce initial knowledge of the system/problem. Extensive experimental study shows that HBF neural network trained with EIF achieves same prediction error and compactness of network topology when compared to EKF, but without the need to know initial state uncertainty, which is its main advantage over EKF

Anuário Científico – 2009 & 2010 Resumos de Artigos, Comunicações, Teses, Patentes, Livros e Monografias de Mestrado

O Conselho Técnico-Científico do Instituto Superior de Engenharia de Lisboa (ISEL), na senda da consolidação da divulgação do conhecimento e da ciência desenvolvidos pelo nosso corpo docente, propõe-se publicar mais uma edição do Anuário Científico, relativa à produção científica de 2009 e 2010. A investigação, enquanto vertente estratégica do Instituto Superior de Engenharia de Lisboa (ISEL), tem concorrido para o seu reconhecimento nacional e internacional como instituição de referência e de qualidade na área do ensino das engenharias. É também nesta vertente que o ISEL consubstancia a sua ligação à sociedade portuguesa e internacional através da transferência de tecnologia e de conhecimento, resultantes da sua atividade científica e pedagógica, contribuindo para o seu desenvolvimento e crescimento de forma sustentada. São parte integrante do Anuário Científico todos os conteúdos com afiliação ISEL resultantes de resumos de artigos publicados em livros, revistas e atas de congressos que os docentes do ISEL apresentaram em fóruns e congressos nacionais e internacionais, bem como teses e patentes. Desde 2002, ano da publicação da primeira edição, temos assistido a uma evolução crescente do número de publicações de conteúdos científicos, fruto do trabalho desenvolvido pelos docentes que se têm empenhado com afinco e perseverança. Contudo, nestes dois anos (2009 e 2010) constatou-se um decréscimo no número de publicações, principalmente em 2010. Uma das causas poderá estar diretamente relacionada com a redução do financiamento ao ensino superior uma vez que limita toda a investigação no âmbito da atividade de I&D e da produção científica. Na sequência da implementação do Processo de Bolonha em 2006, o ISEL promoveu a criação de cursos de Mestrado disponibilizando uma oferta educativa mais completa e diversificada aos seus alunos, mas também de outras instituições, dotando-os de competências inovadoras apropriadas ao mercado de trabalho que hoje se carateriza mais competitivo e dinâmico. Terminados os períodos escolar e de execução das monografias dos alunos, os resumos destas são igualmente parte integrante deste Anuário, no que concerne à conclusão dos Mestrados em 2009 e 2010.A fim de permitir uma maior acessibilidade à comunidade científica e à sociedade civil, o Anuário Científico será editado de ora avante em formato eletrónico. Excecionalmente esta edição contempla publicações referentes a dois anos – 2009 e 2010