Energy-Efficient, Reliable and QoS-Aware Task Mapping on Cyber-Physical Systems

Cyber-Physical Systems (CPS) usually consist of a set of embedded systems (CPS nodes) connected through wireless communication, providing multiple functionalities that support different types of applications. During CPS deployment, application tasks are mapped on the CPS nodes with the objective of enhancing real-time performance, energy efficiency, and execution reliability. To satisfy these requirements, effective task mapping approaches should be designed based on different types of tasks, platforms, applications, and system requirements. In this paper, we provide a comprehensive survey regarding the task mapping methods in CPS

Scheduling Mandatory-Optional Real-Time Tasks in Homogeneous Multi-Core Systems with Energy Constraints Using Bio-Inspired Meta-Heuristics

In this paper we present meta-heuristics to solve the energy aware reward based scheduling of real-time tasks with mandatory and optional parts in homogeneous multi-core processors. The problem is NP-Hard. An objective function to maximize the performance of the system considering the execution of optional parts, the benefits of slowing down the processor and a penalty for changing the operation power-mode is introduced together with a set of constraints that guarantee the real-time performance of the system. The meta-heuristics are the bio-inspired methods Particle Swarm Optimization and Genetic Algorithm. Experiments are made to evaluate the proposed algorithms using a set of synthetic systems of tasks. As these have been used previously with an Integer Lineal Programming approach, the results are compared and show that the solutions obtained with bio-inspired methods are within the Pareto frontier and obtained in less time. Finally, precedence related tasks systems are analyzed and the meta-heuristics proposed are extended to solve also this kind of systems. The evaluation is made by solving a traditional example of the real-time precedence related tasks systems on multiprocessors. The solutions obtained through the methods proposed in this paper are good and show that the methods are competitive. In all cases, the solutions are similar to the ones provided by other methods but obtained in less time and with fewer iterations.Fil: Micheletto, Matías Javier. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Ciencias e Ingeniería de la Computación; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; ArgentinaFil: Santos, Rodrigo Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Ciencias e Ingeniería de la Computación; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; ArgentinaFil: Orozco, Javier Dario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Ciencias e Ingeniería de la Computación; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; Argentin

CPS에서의 물리 에러를 방지하는 안전 보장 메커니즘

학위논문(석사) -- 서울대학교대학원 : 공과대학 컴퓨터공학부, 2023. 2. 이창건.This paper considers a cyber-physical system with a so-called self-looping node that repeats the inner-loop for physical situation awareness, i.e., more loops for more harsh physical situations. Regarding such a self-looping node, we observe the existence of physical errors that make the looping useless and eventually cause a critical failure. To prevent such a critical failure despite a physical error, this paper proposes a novel mechanism by introducing time wall and safety backup. The time wall limits the time budget for the self-looping node so as to switch to the safety backup while still meeting the deadline to prevent critical failure despite physical errors. Our experiments through both simulation and actual implementation show that the proposed mechanism gives a comparable accuracy with the existing methods in normal cases while completely preventing critical failure in physical error cases.본 논문은 물리 상황 인지를 위해 내부 루프를 반복하는 자기반복 모듈(self-looping module)이 있는 사이버 물리 시스템을 고려한다. 자기반복 모듈은 더 높은 정확도를 위해 내부 루프를 반복하지만, 설계 단계에서 고려되지 못한 물리 환경을 마주하게 되면 루프를 반복하더라도 목표 정확도에 도달하지 못하는 물리 에러(physical error) 상황이 발생할 수 있다. 문제는 현재의 시스템의 경우 자기반복 모듈이 물리 에러를 인지하지 못하기 때문에 계속해서 루프를 반복하게 되고, 데드라인을 놓치는 등 시스템 자체의 치명적인 오류로 이어진다는 것이다. 본 논문에서는 물리 에러 상황에서도 최소한의 안전을 보장하기 위해 시간 장벽(time wall)과 안전 백업(safety backup)을 도입한 새로운 메커니즘을 제안한다. 시간 장벽은 자기반복 모듈의 최대 수행 시간으로, 자기반복 모듈이 시간 장벽만큼 실행했는데도 목표 정확도에 도달하지 못하면 안전 백업 모드로 전환한다. 본 논문은 시뮬레이션과 실제 자율주행 소프트웨어인 Autoware에 제안하는 메커니즘을 적용하여 제안하는 메커니즘이 치명적 오류를 완전히 방지하면서, 실제 자율주행 소프트웨어에도 적용 가능함을 보였다.1 Introduction 1 2 Related Work 5 3 Task and Resource Model 6 4 Safety Guarantee Mechanism Against Physical Errors 9 5 Classic Bound based Budget Analysis 13 5.1 Some Useful Computations on DAGs 14 5.2 Simple Solution 15 5.3 Solution with LP 18 6 CPC based Budget Analysis 21 6.1 Initial Budget Calculation 24 6.2 Binary Search for Finding the Optimal Budget 26 7 Generalize to Multiple Self-looping Nodes 30 7.1 Ambiguity in multiple self-looping nodes 30 7.2 Multiple Self-Looping Nodes: A Formal Model 32 7.3 Multiple self-looping nodes: Computing WCETs 34 8 Evaluation 37 8.1 Simulation with Synthetic DAG Workload 37 8.2 Implementation 42 9 Conclusion 46 9.1 Summary 46 9.2 Future Work 46 References 48석

Towards Computational Efficiency of Next Generation Multimedia Systems

To address throughput demands of complex applications (like Multimedia), a next-generation system designer needs to co-design and co-optimize the hardware and software layers. Hardware/software knobs must be tuned in synergy to increase the throughput efficiency. This thesis provides such algorithmic and architectural solutions, while considering the new technology challenges (power-cap and memory aging). The goal is to maximize the throughput efficiency, under timing- and hardware-constraints

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems

Controllable QoS for Imprecise Computation Tasks on DVFS Multicores with Time and Energy Constraints

International audienceMulticore architectures have been used to enhance computing capabilities, but the energy consumption is still an important concern. Embedded application domains usually require less accurate, but always in-time, results. Imprecise Computation (IC) can be used to divide a task into a mandatory subtask providing a baseline QoS and an optional subtask that further increases the baseline QoS. This work aims at maximizing the system QoS by solving task mapping and DVFS for dependent IC-tasks under real-time and energy constraints. Compared with existing approaches, we consider the joint-design problem, where task-to-processor allocation, frequency-to-task assignment, task scheduling and task adjustment are optimized simultaneously. The joint-design problem is formulated as an N P-hard Mixed-Integer Non-Linear Programming and it is safely transformed to a Mixed-Integer Linear Programming (MILP) without performance degradation. Two methods (basic and accelerated version) are proposed to find the optimal solution to MILP problem. They are based on problem decomposition and provide a controllable way to trade-off the quality of the solution and the computational complexity. The optimality of the proposed methods is proved rigorously, and the experimental results show reduced computation time (23.7% in average) compared with existing optimal methods