The use of power gyrator structures as energy processing cells in photovoltaic solar facilities

This paper will provide a classification of high efficiency switching power-gyrator structures and their use as cells for energy processing in photovoltaic solar facilities. Having into account the properties of these topologies presented in the article, their inclusion in solar facilities allows increasing the performance of the whole installation. Thus, the design, simulation and implementation of a G-type power gyrator are carried out throughout the text. In addition, in order to obtain the maximum power from the photovoltaic solar panel, a maximum power point tracking (MPPT) is mandatory in the energy processing path. Therefore, the practical implementation carried out includes a control loop of the power gyrator in order to track the aforementioned maximum power point of the photovoltaic solar panel.Postprint (published version

The use of power DC-DC converters and gyrator structures for energy processing

This article provides a classification of high efficiency switching power-gyrator structures and their use as cells for energy processing in photovoltaic solar facilities. Having into account the properties of these topologies presented in the article, their inclusion in solar facilities allows increasing the performance of the whole installation. Thus, the design, simulation and implementation of a G-type power gyrator are carried out throughout the text. In addition, in order to obtain the maximum power from the photovoltaic solar panel, a maximum power point tracking (MPPT) is mandatory in the energy processing path. Therefore, the practical implementation carried out includes a control loop of the power gyrator in order to track the aforementioned maximum power point of the photovoltaic solar panel.Postprint (published version

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

On the Design of Voltage-Controlled Sinusoidal Oscillators Using OTA's

A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTA's) and capacitors is discussed in this paper. Two classical oscillator models, i.e., quadrature and bandpass-based, are employed to generate several oscillator structures. They are very appropriate for silicon monolithic implementations. The resulting oscillation frequencies are proportional to the transconductance of the OTA and this makes the reported structures well-suited for building voltage controlled oscillators (VCO's). Amplitude stabilization circuits using both automatic gain control (AGC) mechanisms and limitation schemes are presented which are compatible with the transconductance amplifier capacitor oscillator (TACO). Experimental results from bipolar breadboard and CMOS IC prototypes are included showing good potential of OTA-based oscillators for high frequency VCO operation.Comisión Interministerial de Ciencia y Tecnología ME87-000

Wideband Self-Adaptive RF Cancellation Circuit for Full-Duplex Radio: Operating Principle and Measurements

This paper presents a novel RF circuit architecture for self-interference cancellation in inband full-duplex radio transceivers. The developed canceller is able to provide wideband cancellation with waveform bandwidths in the order of 100 MHz or beyond and contains also self-adaptive or self-healing features enabling automatic tracking of time-varying self-interference channel characteristics. In addition to architecture and operating principle descriptions, we also provide actual RF measurements at 2.4 GHz ISM band demonstrating the achievable cancellation levels with different bandwidths and when operating in different antenna configurations and under low-cost highly nonlinear power amplifier. In a very challenging example with a 100 MHz waveform bandwidth, around 41 dB total cancellation is obtained while the corresponding cancellation figure is close to 60 dB with the more conventional 20 MHz carrier bandwidth. Also, efficient tracking in time-varying reflection scenarios is demonstrated.Comment: 7 pages, to be presented in 2015 IEEE 81st Vehicular Technology Conferenc