Design and implementation of a fault-tolerant multimedia network and a local map based (LMB) self-healing scheme for arbitrary topology networks.

by Arion Ko Kin Wa.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 101-[106]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview --- p.1Chapter 1.2 --- Service Survivability Planning --- p.2Chapter 1.3 --- Categories of Outages --- p.3Chapter 1.4 --- Goals of Restoration --- p.4Chapter 1.5 --- Technology Impacts on Network Survivability --- p.5Chapter 1.6 --- Performance Models and Measures in Quantifying Network Sur- vivability --- p.6Chapter 1.7 --- Organization of Thesis --- p.6Chapter 2 --- Design and Implementation of A Survivable High-Speed Mul- timedia Network --- p.8Chapter 2.1 --- An Overview of CUM LAUDE NET --- p.8Chapter 2.2 --- The Network Architecture --- p.9Chapter 2.2.1 --- Architectural Overview --- p.9Chapter 2.2.2 --- Router-Node Design --- p.11Chapter 2.2.3 --- Buffer Allocation --- p.12Chapter 2.2.4 --- Buffer Transmission Priority --- p.14Chapter 2.2.5 --- Congestion Control --- p.15Chapter 2.3 --- Protocols --- p.16Chapter 2.3.1 --- Design Overview --- p.16Chapter 2.3.2 --- ACTA - The MAC Protocol --- p.17Chapter 2.3.3 --- Protocol Layering --- p.18Chapter 2.3.4 --- "Segment, Datagram and Packet Format" --- p.20Chapter 2.3.5 --- Fast Packet Routing --- p.22Chapter 2.3.6 --- Local Host NIU --- p.24Chapter 2.4 --- The Network Restoration Strategy --- p.25Chapter 2.4.1 --- The Dual-Ring Model and Assumptions --- p.26Chapter 2.4.2 --- Scenarios of Network Failure and Remedies --- p.26Chapter 2.4.3 --- Distributed Fault-Tolerant Algorithm --- p.26Chapter 2.4.4 --- Distributed Auto-Healing Algorithm --- p.28Chapter 2.4.5 --- The Network Management Signals --- p.31Chapter 2.5 --- Performance Evaluation --- p.32Chapter 2.5.1 --- Restoration Time --- p.32Chapter 2.5.2 --- Reliability Measures --- p.34Chapter 2.5.3 --- Network Availability During Restoration --- p.41Chapter 2.6 --- The Prototype --- p.42Chapter 2.7 --- Technical Problems Encountered --- p.45Chapter 2.8 --- Chapter Summary and Future Development --- p.46Chapter 3 --- A Simple Experimental Network Management Software - NET- MAN --- p.48Chapter 3.1 --- Introduction to NETMAN --- p.48Chapter 3.2 --- Network Management Basics --- p.49Chapter 3.2.1 --- The Level of Management Protocols --- p.49Chapter 3.2.2 --- Architecture Model --- p.51Chapter 3.2.3 --- TCP/IP Network Management Protocol Architecture --- p.53Chapter 3.2.4 --- A Standard Network Management Protocol On Internet - SNMP --- p.54Chapter 3.2.5 --- A Standard For Managed Information --- p.55Chapter 3.3 --- The CUM LAUDE Network Management Protocol Suite (CNMPS) --- p.56Chapter 3.3.1 --- The Architecture --- p.53Chapter 3.3.2 --- Goals of the CNMPS --- p.59Chapter 3.4 --- Highlights of NETMAN --- p.61Chapter 3.5 --- Functional Descriptions of NETMAN --- p.63Chapter 3.5.1 --- Topology Menu --- p.64Chapter 3.5.2 --- Fault Manager Menu --- p.65Chapter 3.5.3 --- Performance Meter Menu --- p.65Chapter 3.5.4 --- Gateway Utility Menu --- p.67Chapter 3.5.5 --- Tools Menu --- p.67Chapter 3.5.6 --- Help Menu --- p.68Chapter 3.6 --- Chapter Summary --- p.68Chapter 4 --- A Local Map Based (LMB) Self-Healing Scheme for Arbitrary Topology Networks --- p.70Chapter 4.1 --- Introduction --- p.79Chapter 4.2 --- An Overview of Existing DCS-Based Restoration Algorithms --- p.72Chapter 4.3 --- The Network Model and Assumptions --- p.74Chapter 4.4 --- Basics of the LMB Scheme --- p.75Chapter 4.4.1 --- Restoration Concepts --- p.75Chapter 4.4.2 --- Terminology --- p.76Chapter 4.4.3 --- Algorithm Parameters --- p.77Chapter 4.5 --- Performance Assessments --- p.78Chapter 4.6 --- The LMB Network Restoration Scheme --- p.80Chapter 4.6.1 --- Initialization - Local Map Building --- p.80Chapter 4.6.2 --- The LMB Restoration Messages Set --- p.81Chapter 4.6.3 --- Phase I - Local Map Update Phase --- p.81Chapter 4.6.4 --- Phase II - Update Acknowledgment Phase --- p.82Chapter 4.6.5 --- Phase III - Restoration and Confirmation Phase --- p.83Chapter 4.6.6 --- Phase IV - Cancellation Phase --- p.83Chapter 4.6.7 --- Re-Initialization --- p.84Chapter 4.6.8 --- Path Route Monitoring --- p.84Chapter 4.7 --- Performance Evaluation --- p.84Chapter 4.7.1 --- The Testbeds --- p.84Chapter 4.7.2 --- Simulation Results --- p.86Chapter 4.7.3 --- Storage Requirements --- p.89Chapter 4.8 --- The LMB Scheme on ATM and SONET environment --- p.92Chapter 4.9 --- Future Work --- p.94Chapter 4.10 --- Chapter Summary --- p.94Chapter 5 --- Conclusion and Future Work --- p.96Chapter 5.1 --- Conclusion --- p.95Chapter 5.2 --- Future Work --- p.99Bibliography --- p.101Chapter A --- Derivation of Communicative Probability --- p.107Chapter B --- List of Publications --- p.11

NASA SERC 1990 Symposium on VLSI Design

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ENERGY-EFFICIENT FEATURE EXTRACTION ENGINE AND SECURE CHIP IDENTIFICATION FOR UBIQUITOUS SURVEILLANCE

Ph.DDOCTOR OF PHILOSOPH

Measurements, Models, Systems and Design

531 s.

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs