615 research outputs found
A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
This paper propose a decoder architecture for low-density parity-check
convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a
quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure,
the proposed LDPCCC decoder adopts a dynamic message storage in the memory and
uses a simple address controller. The decoder efficiently combines the memories
in the pipelining processors into a large memory block so as to take advantage
of the data-width of the embedded memory in a modern field-programmable gate
array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix
FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz.
Moreover, the decoder displays an excellent error performance of lower than
at a bit-energy-to-noise-power-spectral-density ratio () of
3.55 dB.Comment: accepted to IEEE Transactions on Circuits and Systems
A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes
Non-binary low-density parity-check codes are robust to various channel
impairments. However, based on the existing decoding algorithms, the decoder
implementations are expensive because of their excessive computational
complexity and memory usage. Based on the combinatorial optimization, we
present an approximation method for the check node processing. The simulation
results demonstrate that our scheme has small performance loss over the
additive white Gaussian noise channel and independent Rayleigh fading channel.
Furthermore, the proposed reduced-complexity realization provides significant
savings on hardware, so it yields a good performance-complexity tradeoff and
can be efficiently implemented.Comment: Partially presented in ICNC 2012, International Conference on
Computing, Networking and Communications. Accepted by IEEE Transactions on
Communication
Spatially Coupled Codes and Optical Fiber Communications: An Ideal Match?
In this paper, we highlight the class of spatially coupled codes and discuss
their applicability to long-haul and submarine optical communication systems.
We first demonstrate how to optimize irregular spatially coupled LDPC codes for
their use in optical communications with limited decoding hardware complexity
and then present simulation results with an FPGA-based decoder where we show
that very low error rates can be achieved and that conventional block-based
LDPC codes can be outperformed. In the second part of the paper, we focus on
the combination of spatially coupled LDPC codes with different demodulators and
detectors, important for future systems with adaptive modulation and for
varying channel characteristics. We demonstrate that SC codes can be employed
as universal, channel-agnostic coding schemes.Comment: Invited paper to be presented in the special session on "Signal
Processing, Coding, and Information Theory for Optical Communications" at
IEEE SPAWC 201
Ultra-low power LDPC decoder design with high parallelism for wireless communication system
制度:新 ; 報告番号:甲3423号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574
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