301 research outputs found
An Iteratively Decodable Tensor Product Code with Application to Data Storage
The error pattern correcting code (EPCC) can be constructed to provide a
syndrome decoding table targeting the dominant error events of an inter-symbol
interference channel at the output of the Viterbi detector. For the size of the
syndrome table to be manageable and the list of possible error events to be
reasonable in size, the codeword length of EPCC needs to be short enough.
However, the rate of such a short length code will be too low for hard drive
applications. To accommodate the required large redundancy, it is possible to
record only a highly compressed function of the parity bits of EPCC's tensor
product with a symbol correcting code. In this paper, we show that the proposed
tensor error-pattern correcting code (T-EPCC) is linear time encodable and also
devise a low-complexity soft iterative decoding algorithm for EPCC's tensor
product with q-ary LDPC (T-EPCC-qLDPC). Simulation results show that
T-EPCC-qLDPC achieves almost similar performance to single-level qLDPC with a
1/2 KB sector at 50% reduction in decoding complexity. Moreover, 1 KB
T-EPCC-qLDPC surpasses the performance of 1/2 KB single-level qLDPC at the same
decoder complexity.Comment: Hakim Alhussien, Jaekyun Moon, "An Iteratively Decodable Tensor
Product Code with Application to Data Storage
Concatenated Turbo/LDPC codes for deep space communications: performance and implementation
Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals. Most of them rely on the concatenation of different codes that leads to high hardware implementation complexity and poor resource sharing. This work proposes a scheme based on the concatenation of non-custom LDPC and turbo codes that achieves excellent error correction performance. Moreover, since both LDPC and turbo codes can be decoded with the BCJR algorithm, our preliminary results show that an efficient hardware architecture with high resource reuse can be designe
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