New Algorithms for High-Throughput Decoding with Low-Density Parity-Check Codes using Fixed-Point SIMD Processors

Most digital signal processors contain one or more functional units with a single-instruction, multiple-data architecture that supports saturating fixed-point arithmetic with two or more options for the arithmetic precision. The processors designed for the highest performance contain many such functional units connected through an on-chip network. The selection of the arithmetic precision provides a trade-off between the task-level throughput and the quality of the output of many signal-processing algorithms, and utilization of the interconnection network during execution of the algorithm introduces a latency that can also limit the algorithm\u27s throughput. In this dissertation, we consider the turbo-decoding message-passing algorithm for iterative decoding of low-density parity-check codes and investigate its performance in parallel execution on a processor of interconnected functional units employing fast, low-precision fixed-point arithmetic. It is shown that the frequent occurrence of saturation when 8-bit signed arithmetic is used severely degrades the performance of the algorithm compared with decoding using higher-precision arithmetic. A technique of limiting the magnitude of certain intermediate variables of the algorithm, the extrinsic values, is proposed and shown to eliminate most occurrences of saturation, resulting in performance with 8-bit decoding nearly equal to that achieved with higher-precision decoding. We show that the interconnection latency can have a significant detrimental effect of the throughput of the turbo-decoding message-passing algorithm, which is illustrated for a type of high-performance digital signal processor known as a stream processor. Two alternatives to the standard schedule of message-passing and parity-check operations are proposed for the algorithm. Both alternatives markedly reduce the interconnection latency, and both result in substantially greater throughput than the standard schedule with no increase in the probability of error

Conception Avancée des codes LDPC binaires pour des applications pratiques

The design of binary LDPC codes with low error floors is still a significant problem not fully resolved in the literature. This thesis aims to design optimal/optimized binary LDPC codes. We have two main contributions to build the LDPC codes with low error floors. Our first contribution is an algorithm that enables the design of optimal QC-LDPC codes with maximum girth and mini-mum sizes. We show by simulations that our algorithm reaches the minimum bounds for regular QC-LDPC codes (3, d c ) with low d c . Our second contribution is an algorithm that allows the design optimized of regular LDPC codes by minimizing dominant trapping-sets/expansion-sets. This minimization is performed by a predictive detection of dominant trapping-sets/expansion-sets defined for a regular code C(d v , d c ) of girth g t . By simulations on different rate codes, we show that the codes designed by minimizing dominant trapping-sets/expansion-sets have better performance than the designed codes without taking account of trapping-sets/expansion-sets. The algorithms we proposed are based on the generalized RandPEG. These algorithms take into account non-cycles seen in the case of quasi-cyclic codes to ensure the predictions.La conception de codes LDPC binaires avec un faible plancher d’erreurs est encore un problème considérable non entièrement résolu dans la littérature. Cette thèse a pour objectif la conception optimale/optimisée de codes LDPC binaires. Nous avons deux contributions principales pour la construction de codes LDPC à faible plancher d’erreurs. Notre première contribution est un algorithme qui permet de concevoir des codes QC-LDPC optimaux à large girth avec les tailles minimales. Nous montrons par des simulations que notre algorithme atteint les bornes minimales fixées pour les codes QC-LDPC réguliers (3, d c ) avec d c faible. Notre deuxième contribution est un algorithme qui permet la conception optimisée des codes LDPC réguliers en minimisant les trapping-sets/expansion-sets dominants(es). Cette minimisation s’effectue par une détection prédictive des trapping-sets/expansion-sets dominants(es) définies pour un code régulier C(d v , d c ) de girth gt . Par simulations sur des codes de rendement différent, nous montrons que les codes conçus en minimisant les trapping-sets/expansion-sets dominants(es) ont de meilleures performances que les codes conçus sans la prise en compte des trapping-sets/expansion-sets. Les algorithmes que nous avons proposés se basent sur le RandPEG généralisé. Ces algorithmes prennent en compte les cycles non-vus dans le cas des codes quasi-cycliques pour garantir les prédictions