Two-Level Rectilinear Steiner Trees

Given a set $P$ of terminals in the plane and a partition of $P$ into $k$ subsets $P_1, ..., P_k$, a two-level rectilinear Steiner tree consists of a rectilinear Steiner tree $T_i$ connecting the terminals in each set $P_i$ ($i=1,...,k$) and a top-level tree $T_{top}$ connecting the trees $T_1, ..., T_k$. The goal is to minimize the total length of all trees. This problem arises naturally in the design of low-power physical implementations of parity functions on a computer chip. For bounded $k$ we present a polynomial time approximation scheme (PTAS) that is based on Arora's PTAS for rectilinear Steiner trees after lifting each partition into an extra dimension. For the general case we propose an algorithm that predetermines a connection point for each $T_i$ and $T_{top}$ ($i=1,...,k$). Then, we apply any approximation algorithm for minimum rectilinear Steiner trees in the plane to compute each $T_i$ and $T_{top}$ independently. This gives us a $2.37$-factor approximation with a running time of $\mathcal{O}(|P|\log|P|)$ suitable for fast practical computations. The approximation factor reduces to $1.63$ by applying Arora's approximation scheme in the plane

Fixed-Parameter Algorithms for Rectilinear Steiner tree and Rectilinear Traveling Salesman Problem in the plane

Given a set $P$ of $n$ points with their pairwise distances, the traveling salesman problem (TSP) asks for a shortest tour that visits each point exactly once. A TSP instance is rectilinear when the points lie in the plane and the distance considered between two points is the $l_1$ distance. In this paper, a fixed-parameter algorithm for the Rectilinear TSP is presented and relies on techniques for solving TSP on bounded-treewidth graphs. It proves that the problem can be solved in $O\left(nh7^h\right)$ where $h \leq n$ denotes the number of horizontal lines containing the points of $P$. The same technique can be directly applied to the problem of finding a shortest rectilinear Steiner tree that interconnects the points of $P$ providing a $O\left(nh5^h\right)$ time complexity. Both bounds improve over the best time bounds known for these problems.Comment: 24 pages, 13 figures, 6 table

Flip Distance Between Triangulations of a Simple Polygon is NP-Complete

Let T be a triangulation of a simple polygon. A flip in T is the operation of removing one diagonal of T and adding a different one such that the resulting graph is again a triangulation. The flip distance between two triangulations is the smallest number of flips required to transform one triangulation into the other. For the special case of convex polygons, the problem of determining the shortest flip distance between two triangulations is equivalent to determining the rotation distance between two binary trees, a central problem which is still open after over 25 years of intensive study. We show that computing the flip distance between two triangulations of a simple polygon is NP-complete. This complements a recent result that shows APX-hardness of determining the flip distance between two triangulations of a planar point set.Comment: Accepted versio

Netlist Decomposition and Candidate Generation for Analog IC Routing

Netlist decomposition and candidate generation is a non-conventional approach in the routing stage of the place and route (PnR) flow. While there has been significant research and advancement in the digital domain for automation with respect to this as well as other techniques, very little work has been done in the analog domain due to its complex constraints and specific requirements. With this proposed method, the most common requirements of Analog circuits are taken into consideration to provide candidate routes for netlists of analog Integrated Chips (IC). Netlist decomposition is an important stage of breaking down multi-pin nets into two-pin nets by adding additional nodes for each net. The proposed method takes into account blockages and constraints such as symmetry and bends to develop a new algorithm using Steiner trees and Hanan grids to generate optimal Steiner points. This method also breaks down multi-pin nets to 3-pin nets which reduces the wirelength and computations significantly. The decomposed net segments are run through Dijkstra algorithm to generate multiple candidates and an Integer Linear programming (ILP) solver is used to pick the best candidates that follow all the constraints and design rules. The experimental results show that overall wirelength is reduced by 5.16% while using 3-pin net decomposition when compared to 2-pin net decomposition. There is also a reduction in the number of metal layers used and the number of Steiner points generated. The method shows lesser computations when compared to other decomposition techniques as it avoids multiple reroutes to obtain Design Rule Check (DRC) clean routes

Netlist Decomposition and Candidate Generation for Analog IC Routing

Netlist decomposition and candidate generation is a non-conventional approach in the routing stage of the place and route (PnR) flow. While there has been significant research and advancement in the digital domain for automation with respect to this as well as other techniques, very little work has been done in the analog domain due to its complex constraints and specific requirements. With this proposed method, the most common requirements of Analog circuits are taken into consideration to provide candidate routes for netlists of analog Integrated Chips (IC). Netlist decomposition is an important stage of breaking down multi-pin nets into two-pin nets by adding additional nodes for each net. The proposed method takes into account blockages and constraints such as symmetry and bends to develop a new algorithm using Steiner trees and Hanan grids to generate optimal Steiner points. This method also breaks down multi-pin nets to 3-pin nets which reduces the wirelength and computations significantly. The decomposed net segments are run through Dijkstra algorithm to generate multiple candidates and an Integer Linear programming (ILP) solver is used to pick the best candidates that follow all the constraints and design rules. The experimental results show that overall wirelength is reduced by 5.16% while using 3-pin net decomposition when compared to 2-pin net decomposition. There is also a reduction in the number of metal layers used and the number of Steiner points generated. The method shows lesser computations when compared to other decomposition techniques as it avoids multiple reroutes to obtain Design Rule Check (DRC) clean routes

Rectilinear Steiner Tree Construction

The Minimum Rectilinear Steiner Tree (MRST) problem is to find the minimal spanning tree of a set of points (also called terminals) in the plane that interconnects all the terminals and some extra points (called Steiner points) introduced by intermediate junctions, and in which edge lengths are measured in the L1 (Manhattan) metric. This is one of the oldest optimization problems in mathematics that has been extensively studied and has been proven to be NP-complete, thus efficient approximation heuristics are more applicable than exact algorithms. In this thesis, we present a new heuristic to construct rectilinear Steiner trees (RSTs) with a close approximation of minimum length in Ο(n log n) time. To this end, we recursively divide a plane into a set of sub-planes of which optimal rectilinear Steiner trees (optRSTs) can be generated by a proposed exact algorithm called Const_optRST. By connecting all the optRSTs of the sub-planes, a sub-optimal MRST is eventually constructed. We show experimentally that for topologies with up to 100 terminals, the heuristic is 1.06 to 3.45 times faster than RMST, which is an efficient algorithm based on Prim’s method, with accuracy improvements varying from 1.31 % to 10.21 %

Subexponential Algorithms for Rectilinear Steiner Tree and Arborescence Problems

A rectilinear Steiner tree for a set T of points in the plane is a tree which connects T using horizontal and vertical lines. In the Rectilinear Steiner Tree problem, input is a set T of n points in the Euclidean plane (R^2) and the goal is to find an rectilinear Steiner tree for T of smallest possible total length. A rectilinear Steiner arborecence for a set T of points and root r in T is a rectilinear Steiner tree S for T such that the path in S from r to any point t in T is a shortest path. In the Rectilinear Steiner Arborescense problem the input is a set T of n points in R^2, and a root r in T, the task is to find an rectilinear Steiner arborescence for T, rooted at r of smallest possible total length. In this paper, we give the first subexponential time algorithms for both problems. Our algorithms are deterministic and run in 2^{O(sqrt{n}log n)} time

An Improved Augmented Line Segment based Algorithm for the Generation of Rectilinear Steiner Minimum Tree

An improved Augmented Line Segment Based (ALSB) algorithm for the construction of Rectilinear Steiner Minimum Tree using augmented line segments is proposed. The proposed algorithm works by incrementally increasing the length of line segments drawn from all the points in four directions. The edges are incrementally added to the tree when two line segments intersect. The reduction in cost is obtained by postponing the addition of the edge into the tree when both the edges (upper and lower L-shaped layouts) are of same length or there is no overlap. The improvement is focused on reduction of the cost of the tree and the number of times the line segments are augmented. Instead of increasing the length of line segments by 1, the line segments length are doubled each time until they cross the intersection point between them. The proposed algorithm reduces the wire length and produces good reduction in the number of times the line segments are incremented. Rectilinear Steiner Minimum Tree has the main application in the global routing phase of VLSI design. The proposed improved ALSB algorithm efficiently constructs RSMT for the set of circuits in IBM benchmark