Embedded intelligence for electrical network operation and control

Integrating multiple types of intelligent, mulitagent data analysis within a smart grid can pave the way for flexible, extensible, and robust solutions to power network management

CPS-Net: In-Network Aggregation for Synchrophasor Applications

Abstract-Synchrophasors are sensors that sample power grids and publish these measurements over a network to a number of grid applications such as voltage monitoring, state estimation, visualization, etc. The sampled data is QoS sensitive and must be delivered reliably with minimal delays to the target applications. However, during network overloads or grid emergencies when the volume of data transmitted is high, it is important to gracefully degrade performance and data stream delivery in an applicationspecific manner. We propose CPS-Net, a flexible 3-layered network architecture that allows application-specified in-network aggregation of synchrophasor data streams during overload. The lowest layer provides basic path-specific QoS while the middle layer provides real-time wide-area publish-subscribe capabilities integrated with traffic engineering of data streams across multiple lower level paths and trees. The top layer provides a distributed stream processing infrastructure for application-specified aggregation functions. During network overload, the lower layer triggers the co-optimization of higher layers and application-specific aggregation of data is performed. The user is presented with a simple stream processing programming model and the details of the network, placement and composition of operators are abstracted away. Initial simulation results, using a voltage stability monitoring smart grid application, show that CPS-Net architecture can gracefully degrade data streams for synchrophasor applications

On minimising the maximum expected verification time

Cyber Physical Systems (CPSs) consist of hardware and software components. To verify that the whole (i.e., software + hardware) system meets the given specifications, exhaustive simulation-based approaches (Hardware In the Loop Simulation, HILS) can be effectively used by first generating all relevant simulation scenarios (i.e., sequences of disturbances) and then actually simulating all of them (verification phase). When considering the whole verification activity, we see that the above mentioned verification phase is repeated until no error is found. Accordingly, in order to minimise the time taken by the whole verification activity, in each verification phase we should, ideally, start by simulating scenarios witnessing errors (counterexamples). Of course, to know beforehand the set of such scenarios is not feasible. In this paper we show how to select scenarios so as to minimise the Worst Case Expected Verification Tim

Strategic Optimization Techniques For FRTU Deployment and Chip Physical Design

Combinatorial optimization is a complex engineering subject. Although formulation often depends on the nature of problems that differs from their setup, design, constraints, and implications, establishing a unifying framework is essential. This dissertation investigates the unique features of three important optimization problems that can span from small-scale design automation to large-scale power system planning: (1) Feeder remote terminal unit (FRTU) planning strategy by considering the cybersecurity of secondary distribution network in electrical distribution grid, (2) physical-level synthesis for microfluidic lab-on-a-chip, and (3) discrete gate sizing in very-large-scale integration (VLSI) circuit. First, an optimization technique by cross entropy is proposed to handle FRTU deployment in primary network considering cybersecurity of secondary distribution network. While it is constrained by monetary budget on the number of deployed FRTUs, the proposed algorithm identi?es pivotal locations of a distribution feeder to install the FRTUs in different time horizons. Then, multi-scale optimization techniques are proposed for digital micro?uidic lab-on-a-chip physical level synthesis. The proposed techniques handle the variation-aware lab-on-a-chip placement and routing co-design while satisfying all constraints, and considering contamination and defect. Last, the first fully polynomial time approximation scheme (FPTAS) is proposed for the delay driven discrete gate sizing problem, which explores the theoretical view since the existing works are heuristics with no performance guarantee. The intellectual contribution of the proposed methods establishes a novel paradigm bridging the gaps between professional communities

Active power sharing and frequency regulation in inverter-based islanded microgrids subject to clock drifts, damage in power links and loss of communications

Tesi en modalitat de compendi de publicacions; hi ha diferents seccions retallades per drets de l'editorMicrogrids (MGs) are small-scale power systems containing storage elements, loads and distributed generators that are interfaced with the electric network via power electronic inverters. When an MG is in islanded mode, its dynamics are no longer dominated by the main grid. Then, inverters, driven by digital processors that may exchange data over digital communication, must act as voltage source inverters (VSIs) to take coordinated actions to ensure power quality and supply. The scope of this thesis is bounded to control strategies for active power sharing and frequency regulation in islanded MGs. The focus is on the analysis of prototype control policies when operating conditions are no longer ideal. In particular, the thesis covers the effect that a) clock drifts of digital processors, b) damage in power transmission lines, and c) failures in digital communications have in control performance. The work is submitted as a compendium of publications, including journal and international conference papers, where two main areas of research can be distinguished. The first area refers to the analysis of the effect that clock drifts have on frequency regulation and active power sharing. VSIs digital processors are equipped with oscillators, which run at not necessarily identical frequencies. As consequence, the local clocks in the physically distributed VSIs may differ. This part, reported in two conference papers and one journal paper, investigates state-of-the-art control policies when clocks of the computational devices drift. The contributions related to this part are a) the reformulation of existing control policies in terms of clock drifts, b) the steady-state analysis of these policies that offers analytical expressions to quantify the impact that drifts have on frequency and active power equilibrium points, c) the closed-loop model capable of accommodating all the policies, d) the stability analysis of the equilibrium points, and e) the experimental results. The second area copes with the analysis of the effect that electrical and communication failures have on frequency regulation and active power sharing. This investigation focuses on distributed/cooperative control policies where each inverter control action is computed using both local measures and data received from other inverters within the MG. This part, reported in one conference paper and two journal papers, investigates two control policies when the considered failures in terms of damage in power links and/or loss of communication between inverters provoke partitions within the MG. The contributions related to this part are a) the formulation of the MG as two connected graphs corresponding to the electrical and communication networks where both type of failures lead to disconnected electrical/communication sub-graphs, named partitions, that co-exist within the MG, b) the closed-loop model integrating the two graph Laplacian matrices, c) the stability analysis that identifies which type of partitions may lead to MG instability, d) the steady-state analysis that indicates how to compute the equilibrium points for the case of stable dynamics, e) a new control strategy based on switched control principles that permits avoiding the instability scenario, and f) the experimental results. For the purpose of verifying the operational performance of the analytical results, diverse experiments on a laboratory MG have been performed. The outcomes obtained are discussed and analyzed in terms of the objectives sought. Finally, conclusions and future research lines complete the thesis.Las microredes (MG) son sistemas de energía a pequeña escala que contienen elementos de almacenamiento, cargas y generadores distribuidos que están conectados con la red eléctrica a través de inversores de potencia. Cuando una MG está en modo aislado, su dinámica no está dominada por la red principal. Así, los inversores, comandados por procesadores digitales que pueden intercambiar información a través de comunicaciones digitales, deben actuar como fuentes de voltaje para ejecutar acciones coordinadas que garanticen el suministro de energía. Esta tesis se enmarca dentro de estrategias de control de última generación para compartir potencia activa y regular frecuencia en MG aisladas basadas en inversores. Su enfoque se centra en analizar estas políticas cuando las condiciones de operación no son ideales. En particular, la tesis cubre el efecto que a) desviaciones del reloj de los procesadores digitales, b) daños en las líneas de transmisión de energía, y c) fallas en las comunicaciones digitales, provocan en el rendimiento de control. El trabajo se presenta como un compendio que incluye publicaciones de revistas y de conferencias internacionales, donde se pueden distinguir dos temas principales de investigación. El primer tema comprende el análisis del efecto que tienen las desviaciones de reloj sobre la regulación de frecuencia y la compartición de potencia activa. Los procesadores de los inversores están equipados con osciladores que funcionan a frecuencias no necesariamente idénticas. Como consecuencia, los relojes locales en los inversores distribuidos físicamente, pueden diferir. Esta parte, descrita a través de dos artículos de conferencia y uno de revista, analiza el comportamiento de las políticas de control cuando los relojes de los dispositivos computacionales se desvían. Las contribuciones relacionadas con este tema son a) reformulación de las políticas de control de última generación en términos de desviaciones de reloj, b) análisis de estado estacionario de estas estrategias que ofrece expresiones analíticas para cuantificar el impacto que las desviaciones de reloj tienen sobre los puntos de equilibrio de frecuencia y potencia activa, c) modelo de lazo cerrado adaptable a todas las políticas, d) análisis de estabilidad de los puntos de equilibrio, y e) resultados experimentales. El segundo tema hace frente al análisis del efecto que las fallas eléctricas y de comunicaciones tienen sobre la regulación de frecuencia y el uso compartido de potencia activa. Esta parte se centra en políticas de control distribuido/cooperativo donde cada acción de control del inversor se calcula utilizando medidas locales y datos recibidos de otros inversores de la MG. Esta parte, descrita a través de un artículo de conferencia y dos de revista, investiga dos políticas de control cuando particiones en la MG son provocadas por daños en los enlaces de alimentación y/o por pérdida de comunicación entre inversores. Las contribuciones relacionadas con este tema son a) formulación de la MG como dos grafos correspondientes a las redes eléctrica y de comunicación donde ambos tipos de fallas conducen a sub-grafos eléctricos/comunicacionales desconectados, llamados particiones, que coexisten dentro de la MG, b) modelo de lazo cerrado que integra las matrices Laplacianas de los dos grafos, c) análisis de estabilidad que identifica las particiones que pueden conducir a inestabilidad en la MG, d) análisis de estado estacionario para calcular puntos de equilibrio cuando la dinámica es estable, e) nueva estrategia basada en principios de control conmutado para evitar el escenario de inestabilidad, y f) resultados experimentales. Con el fin de verificar el rendimiento operativo de los resultados analíticos, se han realizado diversos experimentos sobre una microred de laboratorio, los mismos que se discuten en términos de los objetivos de la tesis. El trabajo finaliza con las conclusionesPostprint (published version

Simulation Based Design and Testing of a Supervisory Controller for Reducing Peak Demand in Buildings

We describe a supervisory control strategy for limiting peak power demand by small and medium commercial buildings while still meeting the business needs of the occupants. The objective of the supervisory control is to operate no more tha

Detection of Adversarial Training Examples in Poisoning Attacks through Anomaly Detection

Machine learning has become an important component for many systems and applications including computer vision, spam filtering, malware and network intrusion detection, among others. Despite the capabilities of machine learning algorithms to extract valuable information from data and produce accurate predictions, it has been shown that these algorithms are vulnerable to attacks. Data poisoning is one of the most relevant security threats against machine learning systems, where attackers can subvert the learning process by injecting malicious samples in the training data. Recent work in adversarial machine learning has shown that the so-called optimal attack strategies can successfully poison linear classifiers, degrading the performance of the system dramatically after compromising a small fraction of the training dataset. In this paper we propose a defence mechanism to mitigate the effect of these optimal poisoning attacks based on outlier detection. We show empirically that the adversarial examples generated by these attack strategies are quite different from genuine points, as no detectability constrains are considered to craft the attack. Hence, they can be detected with an appropriate pre-filtering of the training dataset